1. A logging method that comprises:
receiving at least one of a set of amplitude and phase measurements as a function of azimuthal angle and tool position from a set of receivers having no more than two different receiver orientations in response to signals from a set of transmitters having no more than one transmitter orientation;
determining from said set of measurements at least seven components of a coupling matrix as a function of tool position;
finding at least one of vertical resistivity and anisotropy as a function of tool position from the coupling matrix components; and
storing said vertical resistivity or anisotropy in the form of a log.
2. The method of claim 1, wherein said at least one of a phase and amplitude measurement is at least one of a phase difference between responses of the receiver antennas and an amplitude ratio between responses of the receiver antennas.
3. The method of claim 1, further comprising: averaging measurements in a plurality of bins associated with different azimuthal angles.
4. The method of claim 1, wherein said determining is performed based on a linear system of equations that express a dependence of each receiver’s response on azimuthal angle.
5. The method of claim 1, further comprising geosteering based at least in part on said vertical resistivity or anisotropy as a function of tool position.
6. The method of claim 1, further comprising detecting a bed boundary based at least in part on said vertical resistivity or anisotropy as a function of tool position.
7. The method of claim 1, wherein said determining, finding, and storing are performed by a downhole processor.
8. The method of claim 1, wherein said determining, finding, and storing are performed by a surface computing facility.
9. An electromagnetic resistivity logging tool that comprises:
a rotational position sensor;
a set of receiver antennas, wherein the set of receiver antennas includes at least one receiver antenna in a first receiver orientation and at least one receiver antenna in a second receiver orientation that is different than the first receiver orientation;
a set of transmitter antennas, wherein the set of transmitter antennas includes at least one transmitter antenna in a first transmitter orientation and at least one transmitter antenna in a second transmitter orientation that is different than the first transmitter orientation;
a processor to receive at least one of a phase and amplitude measurement for each receiver antenna in the set of receiver antennas in response to signals from transmitter antennas with no more than two orientations for each of a plurality of azimuthal angles and to calculate at least one component of a coupling matrix using only receiver antennas having the first and second receiver antenna orientations.
10. The system of claim 9, wherein the processor finds at least one of vertical resistivity and anisotropy as a function of tool position from coupling matrix components including the at least one component.
11. The system of claim 9, wherein the processor causes said vertical resistivity or anisotropy to be stored in the form of a log.
12. The system of claim 9, wherein said at least one of a phase and amplitude measurement is at least one of a phase difference between responses of the set of receiver antennas and an amplitude ratio between responses of the set of receiver antennas.
13. The system of claim 9, wherein the processor averages measurements in a plurality of bins associated with different azimuthal angles.
14. The system of claim 9, wherein the processor calculates the at least one component of a coupling matrix based on a linear system of equations that express a dependence of each receiver’s response on azimuthal angle.
15. The system of claim 9, wherein the processor determines a geosteering signal based at least in part on the at least one component of the coupling matrix.
16. The system of claim 10, wherein the processor determines a bed boundary based at least in part on said vertical resistivity or anisotropy as a function of tool position.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated circuit packaging system comprising:
forming a substrate including;
patterning a bonding pad on the substrate,
patterning a first signal trace coupled to the bonding pad,
patterning a second signal trace on the substrate, and
connecting a pedestal on the second signal trace;
mounting an integrated circuit on the substrate; and
coupling an electrical interconnect between the integrated circuit, the bonding pad, the pedestal, or a combination thereof.
2. The system as claimed in claim 1 wherein connecting a pedestal includes:
forming a ball bond on the second signal trace; and
coining the ball bond for creating a flat surface.
3. The system as claimed in claim 1 further comprising forming a staggered second row of the bonding pads for connecting the integrated circuit.
4. The system as claimed in claim 1 wherein forming the substrate includes:
forming the first signal trace on the substrate;
forming the second signal trace adjacent to the first signal trace;
mounting the pedestal on the second signal trace; and
positioning the bonding pad, coupled to the first signal trace, in line with the pedestal.
5. The system as claimed in claim 1 further comprising forming an integrated circuit package by encapsulating the substrate, the integrated circuit, and the electrical interconnect.
6. An integrated circuit packaging system comprising:
forming a substrate including;
patterning a bonding pad on the substrate by applying a foil,
patterning a first signal trace coupled to the bonding pad by plating the first signal trace,
patterning a second signal trace on the substrate adjacent to the first signal trace, and
connecting a pedestal on the second signal trace having a staggered position from the bonding pad;
mounting an integrated circuit on the substrate includes mounting an integrated circuit having a fine pitch array of the contact pads; and
coupling an electrical interconnect between the integrated circuit, the bonding pad, the pedestal, or a combination thereof.
7. The system as claimed in claim 6 wherein connecting a pedestal includes:
forming a ball bond on the second signal trace includes positioning the ball bond in a staggered array; and
coining the ball bond for creating a flat surface.
8. The system as claimed in claim 6 further comprising forming a staggered second row of the bonding pad for connecting the integrated circuit including positioning the staggered second row in the gaps of a first row.
9. The system as claimed in claim 6 wherein forming the substrate includes:
forming the first signal trace on the substrate;
forming the second signal trace adjacent to the first signal trace;
mounting the pedestal on the second signal trace; and
positioning the bonding pad, coupled to the first signal trace, in line with the pedestal including coupling an electrical interconnect having a vertical clearance form the bonding pad.
10. The system as claimed in claim 6 further comprising forming an integrated circuit package by encapsulating the substrate, the integrated circuit, and the electrical interconnect including assembling a printed circuit board with the integrated circuit package.
11. An integrated circuit packaging system comprising:
a substrate including;
a bonding pad on the substrate,
a first signal trace coupled to the bonding pad,
a second signal trace on the substrate, and
a pedestal on the second signal trace;
an integrated circuit mounted on the substrate; and
an electrical interconnect coupled between the integrated circuit, the bonding pad, the pedestal, or a combination thereof.
12. The system as claimed in claim 11 wherein the pedestal connected includes:
a ball bond on the second signal trace; and
the ball bond coined for creating a flat surface.
13. The system as claimed in claim 11 further comprising a staggered second row of the bonding pad for connecting the integrated circuit.
14. The system as claimed in claim 11 wherein the substrate includes:
the first signal trace on the substrate;
the second signal trace adjacent to the first signal trace;
the pedestal mounted on the second signal trace; and
the bonding pad, coupled to the first signal trace, in line with the pedestal.
15. The system as claimed in claim 11 further comprising an integrated circuit package formed by the substrate, the integrated circuit, and the electrical interconnect encapsulated.
16. The system as claimed in claim 11 wherein:
the substrate includes;
the bonding pad formed of a thin foil,
the first signal trace, coupled to the bonding pad, plated,
the second signal trace on the substrate adjacent to the first signal trace, and
the pedestal on the second signal trace having a staggered position from the bonding pad;
the integrated circuit mounted on the substrate includes the integrated circuit having a fine pitch array of the contact pad; and
the electrical interconnect coupled between the integrated circuit, the bonding pad, the pedestal, or a combination thereof.
17. The system as claimed in claim 16 wherein the pedestal includes:
a ball bond on the second signal trace includes the ball bond positioned in a staggered array; and
the ball bond coined for creating a flat surface.
18. The system as claimed in claim 16 further comprising a staggered second row of the bonding pad for connecting the integrated circuit includes the staggered second row positioned in the gaps of the first row.
19. The system as claimed in claim 16 wherein the substrate includes:
the first signal trace on the substrate;
the second signal trace adjacent to the first signal trace;
the pedestal on the second signal trace; and
the bonding pad, coupled to the first signal trace, positioned in line with the pedestal includes an electrical interconnect having a vertical clearance form the bonding pad.
20. The system as claimed in claim 16 further comprising an integrated circuit package formed by the substrate, the integrated circuit, and the electrical interconnect encapsulated includes a printed circuit board assembled with the integrated circuit package.