1. A structure comprising:
a substrate layer;
an array of posts, wherein the array of posts and the substrate layer are integrally formed from a single piece of material comprising a polymer material;
a corresponding array of laterally separate micro devices on the array of posts, wherein each micro device includes a bottom surface that is wider than a corresponding post top surface directly underneath the micro device; and
an array of laterally separate metallization layers between the array of laterally separate micro devices and the array of posts.
2. The structure of claim 1, wherein each of the micro devices are of 1-100 \u03bcm scale.
3. The structure of claim 1, wherein each micro device includes p-n diode layer comprising:
a p-doped layer;
an n-doped layer; and
a quantum well layer between the p-doped layer and the n-doped layer.
4. The structure of claim 1, wherein each of the posts has a height between 0.2-4 \u03bcm.
5. The structure of claim 1, further comprising a dielectric layer spanning the bottom surface of each micro device, side surfaces of each post, and a top surface of the substrate layer.
6. The structure of claim 1, wherein each metallization layer includes a bottom surface that is wider than the corresponding post top surface directly underneath the micro device.
7. The structure of claim 6, wherein the bottom surface of each micro device is wider than a top surface of each corresponding metallization layer.
8. The structure of claim 6, wherein each metallization layer makes ohmic contact with each corresponding micro device.
9. The structure of claim 6, wherein each metallization layer is reflective to light emission.
10. The structure of claim 6, wherein each micro device includes p-n diode layer comprising:
a p-doped layer;
an n-doped layer; and
a quantum well layer between the p-doped layer and the n-doped layer.
11. The structure of claim 1, further comprising an array of laterally separate bonding layers between the array of posts and the array of laterally separate metallization layers.
12. The structure of claim 11, wherein array of laterally separate bonding layers is formed of a metal or metal alloy.
13. The structure of claim 12, wherein the array of laterally separate bonding layers is in direct contact with the array of posts and the array of laterally separate metallization layers.
14. The structure of claim 11, wherein the bonding layer has a liquidus temperature such that the bonding layer melts at a temperature without substantially affecting other components of the laterally separate micro devices.
15. The structure of claim 1, further comprising a dielectric layer spanning the bottom surface of each micro device, a bottom surface of the laterally separate metallization layers, side surfaces of each post, and a top surface of the substrate layer.
16. The structure of claim 3, wherein the quantum well layer has a thickness of less than approximately 0.3 \u03bcm.
17. The structure of claim 3, wherein the p-doped layer has a thickness of approximately 0.1-1 \u03bcm.
18. The structure of claim 3, wherein the n-doped layer has a thickness of approximately 0.1-6 \u03bcm.
19. The structure of claim 3, wherein the p-n diode layer has a thickness of less than approximately 9.3 \u03bcm.
20. The structure of claim 2, comprising millions of laterally separate micro devices on a corresponding millions of posts.
21. The structure of claim 2, comprising hundreds of millions of laterally separate micro devices on a corresponding hundreds of millions of posts.
22. The structure of claim 3, wherein each p-n diode layer comprises a top surface, a bottom surface, and tapered sidewalls.
23. The structure of claim 22, wherein the bottom surface of the p-n diode layer is wider than the top surface of the p-n diode layer.
24. The structure of claim 22, wherein the top surface of the p-n diode layer is wider than the bottom surface of the p-n diode layer.
25. The structure of claim 3, wherein each p-n diode layer comprises a top surface, a bottom surface, and vertical sidewalls.
26. The structure of claim 1, wherein each micro device comprises a micro semiconductor device selected from the group consisting of a diode, transistor, or integrated circuit.
27. The structure of claim 1, wherein each micro device comprises a micro semiconductor device selected from the group consisting of a light emitting diode and laser.
28. The structure of claim 1, wherein the array of posts are formed of a dielectric material.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for processing signals, the method comprising:
performing by one or more processors andor circuits:
receiving a signal via a radio frequency (RF) channel, wherein said RF channel comprises a plurality of frequencies;
computing one or more channel estimate values for a portion of said plurality of frequencies based on said received signal; and
computing one or more subsequent channel estimate values for at least a subsequent portion of said plurality of frequencies by iteratively computing a time domain channel matrix and a frequency domain channel matrix based on said computed one or more channel estimate values and a channel noise value for said RF channel,
wherein iteratively computing the frequency domain channel matrix includes applying a time-to-frequency transformation matrix to the time domain channel matrix, the time-to-frequency transformation matrix being computed using non-pilot tone frequencies.
2. The method according to claim 1, wherein said portion of said plurality of frequencies comprises pilot tone frequencies.
3. The method according to claim 1, further comprising:
determining one or more initial values for said one or more subsequent channel estimate values.
4. The method according to claim 3, wherein said one or more initial values are each equal to 0.
5. The method according to claim 3, wherein computing one or more subsequent channel estimate values includes using a minimum mean square error algorithm.
6. A method for processing signals, the method comprising:
performing by one or more processors andor circuits:
receiving a signal via a radio frequency (RF) channel, wherein said RF channel comprises a plurality of frequencies;
computing one or more channel estimate values for a portion of said plurality of frequencies based on said received signal;
computing one or more subsequent channel estimate values for at least a subsequent portion of said plurality of frequencies based on said computed one or more channel estimate values and a channel noise value for said RF channel;
determining one or more initial values for said one or more subsequent channel estimate values;
computing one or more time domain current iteration values for said RF channel based on said one or more initial values, said one or more channel estimate values and said channel noise value; and
computing one or more frequency domain current iteration values for said at least said subsequent portion of said plurality of frequencies based on said one or more time domain current iteration values and a conversion matrix, wherein said conversion matrix is based on said at least said subsequent portion of said plurality of frequencies.
7. The method according to claim 6, further comprising:
computing one or more time domain subsequent iteration values for said RF channel based on said one or more frequency domain current iteration values, said one or more channel estimate values and said channel noise value.
8. The method according to claim 7, further comprising:
computing one or more frequency domain subsequent iteration values for said at least said subsequent portion of said plurality of frequencies based on said one or more time domain subsequent iteration values and said conversion matrix.
9. The method according to claim 8, further comprising:
computing said one or more subsequent channel estimate values based on said one or more frequency domain subsequent iteration values.
10. The method according to claim 8, further comprising:
computing a channel estimate matrix for said RF channel based on a matrix generated from said one or more frequency domain subsequent iteration values and a matrix generated from said one or more channel estimate values.
11. A system for processing signals, the system comprising:
one or more circuits that enable reception of a signal via a radio frequency (RF) channel, wherein said RF channel comprises a plurality of frequencies;
wherein said one or more circuits enable computation of one or more channel estimate values for a portion of said plurality of frequencies based on said received signal;
wherein said one or more circuits enable computation of one or more subsequent channel estimate values for at least a subsequent portion of said plurality of frequencies by iteratively computing a time domain channel matrix and a frequency domain channel matrix based on said computed one or more channel estimate values and a channel noise value for said RF channel, and
wherein iteratively computing the frequency domain channel matrix includes applying a time-to-frequency transformation matrix to the time domain channel matrix, the time-to-frequency transformation matrix being computed using non-pilot tone frequencies.
12. The system according to claim 11, wherein said portion of said plurality of frequencies comprises pilot tone frequencies.
13. The system according to claim 11, wherein said one or more circuits further enable determination of one or more initial values for said one or more subsequent channel estimate values.
14. The system according to claim 13, wherein said one or more initial values are each equal to 0.
15. The system according to claim 13, wherein said one or more circuits further enable computation of one or more subsequent channel estimate values by using a minimum mean square error algorithm.
16. A system for processing signals, the system comprising:
one or more circuits that enable reception of a signal via a radio frequency (RF) channel, wherein said RF channel comprises a plurality of frequencies;
wherein said one or more circuits enable computation of one or more channel estimate values for a portion of said plurality of frequencies based on said received signal;
wherein said one or more circuits enable computation of one or more subsequent channel estimate values for at least a subsequent portion of said plurality of frequencies based on said computed one or more channel estimate values and a channel noise value for said RF channel;
wherein said one or more circuits enable determination of one or more initial values for said one or more subsequent channel estimate values;
wherein said one or more circuits enable computation of one or more time domain current iteration values for said RF channel based on said one or more initial values, said one or more channel estimate values and said channel noise value; and
wherein said one or more circuits further enable computation of one or more frequency domain current iteration values for said at least said subsequent portion of said plurality of frequencies based on said one or more time domain current iteration values and a conversion matrix, wherein said conversion matrix is based on said at least said subsequent portion of said plurality of frequencies.
17. The system according to claim 16, wherein said one or more circuits further enable computation of one or more time domain subsequent iteration values for said RF channel based on said one or more frequency domain cur-ent iteration values, said one or more channel estimate values and said channel noise value.
18. The system according to claim 17, wherein said one or more circuits further enable computation of one or more frequency domain subsequent iteration values for said at least said subsequent portion of said plurality of frequencies based on said one or more time domain subsequent iteration values and said conversion matrix.
19. The system according to claim 18, wherein said one or more circuits further enable computation of said one or more subsequent charnel estimate values based on said one or more frequency domain subsequent iteration values.
20. The system according to claim 18, wherein said one or more circuits further enable computation of a channel estimate matrix for said RF channel based on a matrix generated from said one or more frequency domain subsequent iteration values and a matrix generated from said one or more channel estimate values.