1. An optical connector assembly comprising:
a plug unit including:
a base portion and a pair of outwardly deflectable beam portions formed on two lateral sides of the base portion, a first latching portion located on an inner side of each of the corresponding beam portions, each of the beam portions including an inner arm unitarily extending directly from the base portion and an outer arm extending from a front end of the inner arm with a slot between the inner arm and the outer arm under condition the first latching portion is located around the front end of the inner arm, inwardly deflecting the outer arm toward the inner arm may result in abutment between the inner arm and the outer arm to form a fulcrum and further an outward movement of the first latching portion in a level manner about the fulcrum; and
a head portion assembled to and in front of the base portion with a spring structure therebewteen under a floating manner; wherein the beam portions guide and align a back-and-forth movement of the head portion relative to the base portion in a front-to-back direction between front and rear positions, and the first latching portion prevents excessive forward movement of the head portion toward an excessive position in front of said front position relative to the base portion when said head portion is located in the front position.
2. The optical connector assembly as claimed in claim 1, wherein the base portion defines a passage through which a plurality of optical fibers extend into the head portion.
3. The optical connector assembly as claimed in claim 1, wherein during mating with a receptacle, the plug has the head portion move around the rear position relative to the base portion for allowing second latching portions of the beam potions to lock into corresponding latching recesses in the receptacle so as to have the plug and the receptacle mated with each other securely.
4. The optical connector assembly as claimed in claim 3, wherein said first latching portions and the second latching portions are same one.
5. The optical connector assembly as claimed in claim 1, wherein the outer arm defines an oblique section behind the fulcrum for deflection of the outer arm.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A programmable logic device comprising:
a master delay-locked loop adapted to receive a reference clock signal and provide a digital control signal, wherein the master delay-locked loop comprises;
a series of delay cells adapted to receive the reference clock signal and provide delayed versions of the reference clock signal;
a first multiplexer adapted to select either the reference clock signal or one of the delayed versions of the reference clock signal and provide a first output signal;
a second multiplexer adapted to select either the reference clock signal or the first output signal and provide a clock output signal from the master delay-locked loop;
a third multiplexer adapted to select either the reference clock signal or the first output signal and provide a second output signal;
a fourth multiplexer adapted to select either the reference clock signal or a feedback signal received by the master delay-locked loop and provide a third output signal; and
a control logic circuit adapted to receive the second output signal and the third output signal and generate the digital control signal;
a plurality of signal paths; and
a plurality of slave delay cells disposed respectively within the plurality of signal paths and adapted to receive the digital control signal and provide a signal delay based on the digital control signal.
2. The programmable logic device of claim 1, wherein the control logic circuit comprises:
a phase detect circuit adapted to receive the second output signal and the third output signal;
a counter coupled to the phase detect circuit and adapted to control a delay applied by the series of delay cells;
an arithmetic logic unit coupled to the counter and adapted to selectively perform an arithmetic operation upon a counter output signal; and
a register coupled to the arithmetic logic unit and adapted to provide the digital control signal.
3. The programmable logic device of claim 2, wherein the register is permitted to change a value of the digital control signal if an update signal received by the register is asserted.
4. The programmable logic device of claim 1, wherein each of the slave delay cells further comprises;
a coarse stage adapted to receive an input signal and provide delayed versions of the input signal;
a first multiplexer adapted to select either the input signal or one of the delayed versions of the input signal and provide a first output signal;
a fine stage coupled to the first multiplexer and adapted to receive the first output signal and provide fine delayed versions of the first output signal; and
a second multiplexer adapted to select either the first output signal or one of he fine delayed versions of the first output signal and provide a second output signal.
5. The programmable logic device of claim 4, wherein each of the slave delay cells further comprises a third multiplexer adapted to receive at least the digital control signal and a first control signal from a memory and provide a second control signal to the first multiplexer and the second multiplexer.
6. The programmable logic device of claim 5, further comprising a second master delay-locked loop adapted to provide a second digital control signal to the third multiplexer, which may be selected as the second control signal.
7. The programmable logic device of claim 1, wherein the master delay-locked loop controls the slave delay cells to cancel or match clock injection delay or provide a fixed delay based on a clock cycle of the reference clock signal.
8. A delay cell architecture comprising:
a master delay cell adapted to receive a reference clock signal and a feedback signal and provide a clock signal and digital control signals, wherein the waster delay cell has means for generating a plurality of delayed versions of the reference clock signal and means for determining a phase between the reference clock signal or one of the plurality of delayed versions of the reference clock signal and the feedback signal or the reference clock signal to determine one or more values for the digital control signals;
a plurality of slave delay cells disposed on a plurality of corresponding signal paths and adapted to receive the digital control signals, wherein each of the slave delay cells has means for receiving an input signal and selectively applying a delayed output signal based on one of the digital control signals;
a second master delay cell; and
a memory adapted to provide a static memory digital control signal, wherein the plurality of slave delay cells is further adapted to receive the digital control signals from the second master delay cell and the memory digital control signal, wherein the delayed output signal is based on the memory digital control signal or the digital control signal from master delay cell or second master delay cell.
9. The delay cell architecture of claim 8, wherein the master delay cell controls a first set of the plurality of slave delay cells to provide a signal delay for a clock signal and the second master delay cell controls a second set of the plurality of slave delay cells to provide a signal delay for a data signal.
10. The delay cell architecture of claim 8, wherein the master delay cell controls the slave delay cells to substantially cancel clock injection delay.
11. A method of inserting a delay into a plurality of signal paths of a programmable logic device, the method comprising:
receiving a reference clock signal;
generating delayed versions of the reference clock signal;
receiving a feedback clock signal;
selecting between the reference clock signal and one of the delayed versions of the reference clock signal to provide a first signal;
selecting between the reference clock signal and the feedback clock signal to provide a second signal;
determining a phase difference between the first signal and the second signal; and
providing one or more control signals based on the determined phase difference to delay cells within the plurality of signal paths.
12. The method of claim 11, further comprising generating a clock signal based on the reference clock signal or one of the delayed versions of the reference clock signal.
13. The method of claim 11, wherein the delay cells provide a coarse delay and a fine delay based on the control signals.
14. The method of claim 11, wherein the control signals may be provided by memory or one or more master delay cells.
15. The method of claim 11, wherein the control signals determine a signal delay for one or more of the delay cells based on a fraction of a clock cycle of the reference clock signal.
16. The method of claim 11, wherein the delay cells provide a signal delay that approximately cancels or matches a path delay.
17. A master delay-locked loop circuit within a programmable logic device, the circuit comprising:
a series of delay cells adapted to receive a reference clock signal and provide delayed versions of the reference clock signal;
a first multiplexer adapted to select either the reference clock signal or one of the delayed versions of the reference clock signal and provide a first output signal;
a second multiplexer adapted to select either the reference clock signal or the first output signal and provide a clock output signal from the master delay-locked loop circuit;
a third multiplexer adapted to select either the reference clock signal or the first output signal and provide a second output signal;
a fourth multiplexer adapted to select either the reference clock signal or a feedback signal received by the master delay-locked loop circuit and provide a third output signal; and
a control logic circuit adapted to receive the second output signal and the third output signal and generate a digital control signal.
18. The circuit of claim 17, wherein the control logic circuit comprises:
a phase detect circuit adapted to receive the second output signal and the third output signal;
a counter coupled to the phase detect circuit and adapted to control a delay applied by the series of delay cells;
an arithmetic logic unit coupled to the counter and adapted to selectively perform an arithmetic operation upon a counter output signal; and
a register coupled to the arithmetic logic unit and adapted to provide the digital control signal.