What is claimed is:
1. (Currently amended) A switch in bipolar technology, comprising:
a first main transistor (1) of a first type connecting an input terminal (IN), intended to be connected to a first terminal of application of a D.C. supply voltage (Vcc), to an output terminal (OUT) intended to be connected to a load (Q) to be supplied;
a second bipolar transistor (2) of the same type as the first one, connected between said input terminal and an input of a current mirror circuit (3, 4) having a copying output connected to the base of the first transistor, the bases of the first and second transistors being interconnected and the first transistor having an emitter surface area greater than the second one;
further comprising a circuit (6) for biasing the second transistor consisting in the copying of the output voltage of the switch on the collector of this second transistor.
2. (Currently amended) The switch of claim 1, wherein said current mirror circuit (3, 4) is formed of a third bipolar transistor (3) of a second type and of a fourth bipolar transistor (4) of the second type connecting the base of the first transistor (1) to a second terminal (M) of application of the supply voltage, the bases of the third and fourth transistors being interconnected to the collector of the third transistor connecting the collector of the second transistor via a fifth bipolar transistor (10) of the first type belonging to the biasing circuit (6).
3. (Currently amended) The switch of claim 2, wherein the fourth transistor (4) has an emitter surface area greater than that of the third transistor (3).
4. (Currently amended) The switch of claim 2 or 3, wherein the biasing circuit further comprises a sixth transistor (11) of the second type connected between said output terminal (OUT) by its emitter and a seventh bipolar transistor (12) of the second type mirror-assembled on said third (3) and fourth (4) transistors, the emitter surface area of the seventh transistor being, preferably, identical to that of the third transistor.
5. (Currently amended) The switch of any of claims 2 to 4 claim 2, wherein a starting current source (7) connects the base of the first transistor (1) to the second terminal of application of the supply voltage.
6. (Currently amended) The switch of any of claims 2 to 5 claim 2, wherein a start-up aid circuit (8) injects a current on the collector of the second transistor (2), the start-up aid circuit being preferably formed of a resistor (R8) in series with an eighth transistor (13) of the first type connected between the input terminal (IN) and said collector of the second transistor, the base of the eighth transistor being connected to the base of the first transistor (1) to inject a current which is an image of the output current.
7. (Currently amended) The switch of any of claims 2 to 6 claim 2, wherein a circuit for limiting the internal current formed, preferably, of a resistor (R9) interposed between the collectors of the fifth (10) and third (3) transistors, and of a ninth transistor (14) for branching the current to ground, is provided.
8. (Currently amended) The switch of any of claims 1 to 7 claim 1, wherein the transistors of the first type are PNP transistors, the transistors of the second type being NPN transistors.
9. (Currently amended) The switch of any of claims 1 to 7 claim 1, wherein the transistors of the first type are NPN-type transistors, the transistors of the second type being PNP-type transistors.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for controlling execution of multiple tasks in a processing circuit including several processing modules, comprising the steps of:
determining temperature-associated information at various areas of the processing circuit; and
in response to temperature-associated information indicating an excessive temperature at an area associated with a first of said processing modules, modifying parameters for executing tasks on one or more adjacent processing modules in order to reduce heat generated by the adjacent processing modules and contributing to the excessive temperature at the first processing module.
2. The method of claim 1 wherein said determining step comprises the step of monitoring operations executed by said modules.
3. The method of claim 1 wherein said determining step comprises the step of calculating power dissipation information at various locations in said processing circuit.
4. The method of claim 1 wherein said determining step comprises the step of calculating a current temperature at various locations in said processing circuit.
5. A method for controlling execution of multiple tasks in a processing circuit including a plurality of processing modules, comprising the steps of:
generating a task allocation scenario for allocating multiple tasks among the plurality of processing modules;
prior to executing the tasks, estimating temperature-associated information for various locations in the processing circuit as would occur if the tasks were executed according to the scenario;
determining whether a temperature threshold would be exceeded by executing the tasks according to the scenario.
6. The method of claim 5 wherein said step of generating a task allocation scenario comprises the step of receiving a task list describing the tasks to be executed and a task model describing the tasks.
7. The method of claim 6 wherein the task model includes initial area-specific power dissipation estimates for each task.
8. A processing circuit including a plurality of processing modules for executing multiple tasks comprising:
circuitry for determining temperature-associated information at various areas of the processing circuit; and
circuitry responsive to temperature-associated information indicating an excessive temperature at an area associated with a first of said processing modules for modifying parameters for executing tasks on one or more adjacent processing modules in order to reduce heat generated by the adjacent processing modules and contributing to the excessive temperature at the first processing module.
9. The processing circuit of claim 8 wherein said determining circuitry comprises circuitry for monitoring operations executed by said processing modules.
10. The processing circuit of claim 8 wherein said determining circuitry comprises circuitry for calculating power dissipation information at various locations in said processing circuit.
11. The processing circuit of claim 8 wherein said determining circuitry comprises circuitry for calculating a current temperature at various locations in said processing circuit.
12. A processing circuit comprising:
a plurality of processing modules for executing multiple tasks; and
circuitry for generating a task allocation scenario for allocating the tasks among the processing modules, estimating temperature-associated information for various locations in the processing circuit as would occur if the tasks were executed according to the scenario and determining whether a temperature threshold would be exceeded if the tasks were to be executed according to the scenario.
13. The processing circuit of claim 12 wherein said circuitry for generating a task allocation scenario comprises circuitry for receiving a task list describing the tasks to be executed and a task model describing the tasks.
14. The processing circuit of claim 13 wherein the task model includes initial area-specific power dissipation estimates for each task.
15. A mobile communications device comprising:
a plurality of processing modules for executing a plurality of tasks;
an antenna for receiving and transmitting signals; and
receivertransmitter circuitry coupled to said antenna for sending and receiving audio and data signals, said receivertransmitter circuitry including a processing circuit comprising:
circuitry for determining temperature-associated information at various areas of the processing circuit; and
circuitry responsive to temperature-associated information indicating an excessive temperature at an area associated with a first of said processing modules for modifying parameters for executing tasks on one or more adjacent processing modules in order to reduce heat generated by the adjacent processing modules and contributing to the excessive temperature at the first processing module.