1. A wafer comprising:
a wafer substrate having a substantially planar surface thereon formed during an initial planarization of a deformable material solidified in contact with a substantially flat planar surface of an object and a final planarization of the deformable material after curing using a chemical mechanical planarization process.
2. The wafer of claim 1, further comprising:
solidifying the deformable material while applying pressure to the object as the object contacts the deformable material.
3. The wafer of claim 1, wherein the object includes the substantially flat planar surface thereon contacting the deformable material.
4. A wafer in a chemical mechanical planarization process comprising:
a wafer substrate having a substantially planar surface thereon formed during an initial planarization of a deformable material solidified in contact with a substantially flat planar surface of an object and a final planarization of the deformable material after curing using a chemical mechanical planarization process.
5. The wafer in a chemical mechanical planarization process of claim 4, further comprising:
solidifying the deformable material while applying pressure to the object as the object contacts the deformable material.
6. The wafer in a chemical mechanical planarization process of claim 4, wherein the object includes the substantially flat planar surface thereon contacting the deformable material.
7. A wafer having at least a portion of at least one integrated circuit formed thereon in a chemical mechanical planarization process comprising:
a wafer substrate having a substantially planar surface thereon formed during an initial planarization of a deformable material solidified in contact with a substantially flat planar surface of an object and a final planarization of the deformable material after curing using a chemical mechanical planarization process.
8. The wafer having at least a portion of at least one integrated circuit formed thereon in a chemical mechanical planarization process of claim 7, further comprising:
solidifying the deformable material while applying pressure to the object as the object contacts the deformable material.
9. The wafer having at least a portion of at least one integrated circuit formed thereon in a chemical mechanical planarization process of claim 7, wherein the object includes the substantially flat planar surface thereon contacting the deformable material.
10. A wafer having at least a portion of at least one integrated circuit formed thereon in at least a portion of a semiconductor device being formed on the wafer, the wafer located in a chemical mechanical planarization process comprising:
a wafer substrate having a substantially planar surface thereon formed during an initial planarization of a deformable material solidified in contact with a substantially flat planar surface of an object and a final planarization of the deformable material after curing using a chemical mechanical planarization process.
11. The wafer having at least a portion of at least one integrated circuit formed thereon in at least a portion of a semiconductor device being formed on the wafer, the wafer located in a chemical mechanical planarization process of claim 10, further comprising:
solidifying the deformable material while applying pressure to the object as the object contacts the deformable material.
12. The wafer having at least a portion of at least one integrated circuit formed thereon in at least a portion of a semiconductor device being formed on the wafer, the wafer located in a chemical mechanical planarization process of claim 10, wherein the object includes the substantially flat planar surface thereon contacting the deformable material.
13. A wafer having at least a portion of at least one integrated circuit formed thereon in at least a portion of a semiconductor device of a plurality of semiconductor devices being formed on the wafer, the wafer located in a chemical mechanical planarization process comprising:
a wafer substrate having a substantially planar surface thereon formed during an initial planarization of a deformable material solidified in contact with a substantially flat planar surface of an object and a final planarization of the deformable material after curing using a chemical mechanical planarization process.
14. The wafer having at least a portion of at least one integrated circuit formed thereon in at least a portion of a semiconductor device of a plurality of semiconductor devices being formed on the wafer, the wafer located in a chemical mechanical planarization process of claim 13, further comprising:
solidifying the deformable material while applying pressure to the object as the object contacts the deformable material.
15. The wafer having at least a portion of at least one integrated circuit formed thereon in at least a portion of a semiconductor device of a plurality of semiconductor devices being formed on the wafer, the wafer located in a chemical mechanical planarization process of claim 13, wherein the object includes the substantially flat planar surface thereon contacting the deformable material.
16. A wafer having at least a portion of at least one integrated circuit formed thereon in at least a portion of a semiconductor device of a plurality of semiconductor devices being formed on the wafer, the wafer located in a planarization process comprising:
a wafer substrate having a substantially planar surface thereon formed during a planarization of a deformable material solidified in contact with a substantially flat planar surface of an object and a final planarization of the deformable material after curing using a chemical mechanical planarization process.
17. The wafer having at least a portion of at least one integrated circuit formed thereon in at least a portion of a semiconductor device of a plurality of semiconductor devices being formed on the wafer, the wafer located in a chemical mechanical planarization process of claim 16, further comprising:
solidifying the deformable material while applying pressure to the object as the object contacts the deformable material.
19. The wafer having at least a portion of at least one integrated circuit formed thereon in at least a portion of a semiconductor device of a plurality of semiconductor devices being formed on the wafer, the wafer located in a chemical mechanical planarization process of claim 16, wherein the object includes the substantially flat planar surface thereon contacting the deformable material.
20. A wafer comprising:
a wafer having a surface thereon formed during an initial planarization of a material solidified in contact with a surface of an object and a final planarization of the material using a chemical mechanical planarization process.
21. The wafer of claim 20, further comprising:
solidifying the material while applying pressure to the object as the object contacts the material.
22. The wafer of claim 20, wherein the surface of the object includes a substantially flat planar surface thereon contacting the material.
23. A wafer in a chemical mechanical planarization process comprising:
a wafer having a surface thereon formed during an initial planarization of a material solidified in contact with a surface of an object and a final planarization of the material using a chemical mechanical planarization process.
24. The wafer in a chemical mechanical planarization process of claim 23, further comprising:
solidifying the material while applying pressure to the object as the object contacts the material.
25. The wafer in a chemical mechanical planarization process of claim 23, wherein the surface of the object includes a substantially flat planar surface thereon contacting the deformable material.
26. A wafer having at least a portion of at least one integrated circuit formed thereon in a chemical mechanical planarization process comprising:
a wafer having a surface thereon formed during an initial planarization of a material solidified in contact with a surface of an object and a final planarization of the material using a chemical mechanical planarization process.
27. The wafer having at least a portion of at least one integrated circuit formed thereon in a chemical mechanical planarization process of claim 26, further comprising:
solidifying the material while applying pressure to the object as the object contacts the material.
28. The wafer having at least a portion of at least one integrated circuit formed thereon in a chemical mechanical planarization process of claim 26, wherein the surface of the object includes a substantially flat planar surface thereon contacting the deformable material.
29. A wafer having at least a portion of at least one integrated circuit formed thereon in at least a portion of a semiconductor device being formed on the wafer, the wafer located in a chemical mechanical planarization process comprising:
a wafer having a surface thereon formed during an initial planarization of a material solidified in contact with a surface of an object and a final planarization of the deformable material using a chemical mechanical planarization process.
30. The wafer having at least a portion of at least one integrated circuit formed thereon in at least a portion of a semiconductor device being formed on the wafer, the wafer located in a chemical mechanical planarization process of claim 29, further comprising:
solidifying the material while applying pressure to the object as the object contacts the material.
31. The wafer having at least a portion of at least one integrated circuit formed thereon in at least a portion of a semiconductor device being formed on the wafer, the wafer located in a chemical mechanical planarization process of claim 29, wherein the surface of the object includes a substantially flat planar surface thereon contacting the material.
32. A wafer having at least a portion of at least one integrated circuit formed thereon in at least a portion of a semiconductor device of a plurality of semiconductor devices being formed on the wafer, the wafer located in a chemical mechanical planarization process comprising:
a wafer having a surface thereon formed during an initial planarization of a material solidified in contact with a surface of an object and a final planarization of the material using a chemical mechanical planarization process.
33. The wafer having at least a portion of at least one integrated circuit formed thereon in at least a portion of a semiconductor device of a plurality of semiconductor devices being formed on the wafer, the wafer located in a chemical mechanical planarization process of claim 32, further comprising:
solidifying the material while applying pressure to the object as the object contacts the material.
34. The wafer having at least a portion of at least one integrated circuit formed thereon in at least a portion of a semiconductor device of a plurality of semiconductor devices being formed on the wafer, the wafer located in a chemical mechanical planarization process of claim 33, wherein the surface of the object includes a substantially flat planar surface thereon contacting the material.
35. A wafer having at least a portion of at least one integrated circuit formed thereon in at least a portion of a semiconductor device of a plurality of semiconductor devices being formed on the wafer, the wafer located in a chemical mechanical planarization process comprising:
a wafer having a surface thereon formed during a planarization of a material solidified in contact with a surface of an object and a final planarization of the material using a chemical mechanical planarization process.
36. The wafer having at least a portion of at least one integrated circuit formed thereon in at least a portion of a semiconductor device of a plurality of semiconductor devices being formed on the wafer, the wafer located in a chemical mechanical planarization process of claim 35, further comprising:
solidifying the material while applying pressure to the object as the object contacts the material.
37. The wafer having at least a portion of at least one integrated circuit formed thereon in at least a portion of a semiconductor device of a plurality of semiconductor devices being formed on the wafer, the wafer located in a chemical mechanical planarization process of claim 35, wherein the surface of the object includes a substantially flat planar surface thereon contacting the material.
38. A semiconductor device comprising:
a portion of a wafer substrate having a substantially planar surface thereon formed during an initial planarization of a deformable material solidified in contact with a substantially flat planar surface of an object and a final planarization of the deformable material after curing using a chemical mechanical planarization process.
39. The semiconductor device of claim 38, further comprising:
solidifying the deformable material while applying pressure to the object as the object contacts the deformable material.
40. The semiconductor device of claim 38, wherein the object includes the substantially flat planar surface thereon contacting the deformable material.
41. A semiconductor device comprising:
a portion of a wafer having a surface thereon formed during an initial planarization of a material solidified in contact with a surface of an object and a final planarization of the material using a chemical mechanical planarization process.
42. The semiconductor device of claim 41, further comprising:
solidifying the material while applying pressure to the object as the object contacts the material.
43. The semiconductor device claim 41, wherein the surface of the object includes a substantially flat planar surface thereon contacting the material.
44. An incomplete semiconductor device comprising:
a portion of a wafer having a substantially planar surface thereon formed during an initial planarization of a material solidified in contact with a surface of an object and a final planarization of the material using a chemical mechanical planarization process.
45. The incomplete semiconductor device of claim 44, further comprising:
solidifying the material while applying pressure to the object as the object contacts the material.
46. The incomplete semiconductor device of claim 44, wherein the surface of the object includes a substantially flat planar surface thereon contacting the material.
47. A semiconductor device in a manufacturing process comprising:
a portion of a wafer having a surface thereon formed during an initial planarization of a material solidified in contact with a surface of an object and a final planarization of the material using a chemical mechanical planarization process.
48. The semiconductor device in a manufacturing process of claim 47, further comprising:
solidifying the material while applying pressure to the object as the object contacts the material.
49. The semiconductor device in a manufacturing process of claim 47, wherein the surface of the object includes a substantially flat planar surface thereon contacting the material.
50. An incomplete semiconductor device in a manufacturing process comprising:
a portion of a wafer having a surface thereon formed during an initial planarization of a material solidified in contact with a surface of an object and a final planarization of the material using a chemical mechanical planarization process.
51. The incomplete semiconductor device in a manufacturing process of claim 50, further comprising:
solidifying the material while applying pressure to the object as the object contacts the material.
52. The incomplete semiconductor device in a manufacturing process of claim 50, wherein the surface of the object includes a substantially flat planar surface thereon contacting the material.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A discharge controller for controlling discharge of a plurality of cells connected in parallel with each other and including a degradation region in an intermediate region, the controller comprising:
a remaining capacity calculation section that calculates remaining capacities for each of the plurality of cells; and
a control section that, after starting discharge of the plurality of cells, stops discharge of one of the cells whose remaining capacity calculated by said remaining capacity calculation section has become equal to a threshold value set in advance based on the upper limit of the degradation region.
2. The discharge controller according to claim 1, wherein said remaining capacity calculation section measures currents flowing from the cells and the time from the start of discharge of the cells, and obtains, as the remaining capacities, values calculated by respectively subtracting the products of multiplication of the measured currents and time from the full-charge capacities of the cells.
3. The discharge controller according to claim 1, wherein said remaining capacity calculation section measures voltages across the cells and obtains the measured voltages as the remaining capacities.
4. The discharge controller according to claim 1, further comprising a storage section that stores the threshold value in advance,
wherein said control section reads out the threshold value stored in said storage section and compares the threshold values with the remaining capacities.
5. The discharge controller according to claim 1, further comprising a storage section that controller according to claim 1, wherein said control section controls discharge and non-discharge of the plurality of cells by opening and closing a plurality of switches for establishing or breaking connections between the plurality of cells and an output terminal through which cells are externally discharged.
6. The discharge controller according to claim 1, further comprising a storage section that controller according to claim 1, wherein said control section performs rotation discharge of the plurality of cells if each of the remaining capacities of the plurality of cells is larger than the threshold value.
7. A discharge control method for controlling discharge of a plurality of cells connected in parallel with each other and including a degradation region in an intermediate region, the method comprising the steps of:
discharging the plurality of cells;
calculating remaining capacities for each of the plurality of cells; and
stopping, after starting discharge of the plurality of cells, discharge of one of the plurality of cells whose remaining capacity calculated has become equal to a threshold value set in advance based on the upper limit of the degradation region.
8. The discharge control method according to claim 7, wherein said calculation step includes measuring currents flowing from the cells and the time from the start of discharge of the cells, and obtaining, as the remaining capacities, values calculated by respectively subtracting the products of multiplication of the measured currents and time from the full-charge capacities of the cells.
9. The discharge control method according to claim 7, wherein said calculation step includes measuring voltages across the cells and obtaining the measured voltages as the remaining capacities.
10. The discharge control method according to claim 7, further comprising the step of performing rotation discharge of the plurality of cells if each of the remaining capacities of the plurality of cells is larger than the threshold value.
11. (canceled)
12. (canceled)
13. (canceled)
14. (canceled)
15. The discharge controller according to claim 1, wherein the cells include a lithium-ion cell that has a manganese-based positive electrode.