1. A method of performing a global timing analysis of a proposed digital circuit comprising:
receiving timing models and said proposed digital circuit, the proposed digital circuit being a periodic circuit;
determining a plurality of modes of circuit operation of said proposed digital circuit;
deriving a sub-circuit corresponding to each of said modes of circuit operation;
performing timing analysis on each of said sub-circuits derived corresponding to each of said modes; and
combining the timing analysis results for said modes to determine an overall maximum circuit delay.
2. The method of claim 1 wherein said proposed digital circuit is received in the form of a circuit graph.
3. The method of claim 2 wherein said circuit graph includes components and interconnections between said components.
4. The method of claim 1 wherein said timing models are received for components and interconnections of said digital circuit.
5. The method of claim 4 wherein said timing models include timing edges and delays.
6. The method of claim 1 wherein said determination of at least one mode of circuit operation is performed by first determining control signals of said digital circuit.
7. The method of claim 6 wherein said control signals are associated with those signals that control the sensitization of circuit paths with large delay.
8. The method of claim 6 wherein said modes of circuit operation include all possible combinations of control signal values.
9. The method of claim 6 wherein said modes of circuit operation are determined such that in each mode, the control signals that influence the sensitization of those circuit paths with large delay that are sensitized in this mode are assigned a 0 or a 1 value.
10. The method of claim 6 wherein said control signal values are one of a \u201c0\u201d or a \u201c1\u201d.
11. The method of claim 1 wherein:
said digital circuit is received in the form of a circuit graph;
said timing models including timing edges and delays; and
said determination of at least one mode of circuit operation is performed by first determining control signals of said digital circuit.
12. The method of claim 11 wherein deriving a sub-circuit for each of said modes is done by:
applying values corresponding to each of said modes to said control signals;
propagating said control signal values through the circuit graph for each of said modes; and
removing disabled timing edges from the circuit graph to create a modified circuit graph for each of said nodes.
13. The method of claim 12 further including:
disabling timing edges including those timing edges through which no signal propagates in each of said modes.
14. The method of claim 1 wherein said timing analysis is performed using Program Evaluation and Review Technique (PERT).
15. The method of claim 1 wherein said step of determining an overall maximum circuit delay includes:
identifying a mode containing a maximum delay.
16. The method of claim 1 wherein the proposed digital circuit comprises a circuit datapath that is controlled by a finite-state machine based controller.
17. A method of performing a global timing analysis of a proposed digital circuit comprising:
receiving timing models and said proposed digital circuit, the proposed digital circuit being produced as a result of software pipelining;
determining a plurality of modes of circuit operation of said proposed digital circuit;
deriving a sub-circuit corresponding to each of said modes of circuit operation;
performing timing analysis on each of said sub-circuits derived corresponding to each of said modes; and
combining the timing analysis results for said modes to determine an overall maximum circuit delay.
18. The method of claim 17 wherein said proposed digital circuit is received in the form of a circuit graph including components and interconnections between said components.
19. The method of claim 18 wherein said timing models are received for said components and interconnections, said timing models including timing edges and delays.
20. The method of claim 17 wherein said determination of at least one mode of circuit operation is performed by first determining control signals of said digital circuit.
21. The method of claim 20 wherein deriving a sub-circuit for each of said modes is done by:
applying values corresponding to each of said modes to said control signals;
propagating said control signal values through the circuit graph for each of said modes; and
removing disabled timing edges from the circuit graph to create a modified circuit graph for each of said nodes.
22. A method of performing a global timing analysis of a proposed digital circuit comprising:
receiving timing models and said proposed digital circuit, the proposed digital circuit being produced as a result of modulo scheduling;
determining a plurality of modes of circuit operation of said proposed digital circuit;
deriving a sub-circuit corresponding to each of said modes of circuit operation;
performing timing analysis on each of said sub-circuits derived corresponding to each of said modes; and
combining the timing analysis results for said modes to determine an overall maximum circuit delay.
23. The method of claim 22 wherein said proposed digital circuit is received in the form of a circuit graph including components and interconnections between said components.
24. The method of claim 23 wherein said timing models are received for said components and interconnections, said timing models including timing edges and delays.
25. The method of claim 22 wherein said determination of at least one mode of circuit operation is performed by first determining control signals of said digital circuit.
26. The method of claim 25 wherein deriving a sub-circuit for each of said modes is done by:
applying values corresponding to each of said modes to said control signals;
propagating said control signal values through the circuit graph for each of said modes; and
removing disabled timing edges from the circuit graph to create a modified circuit graph for each of said nodes.
27. A method of performing a global timing analysis of a proposed digital circuit comprising:
receiving timing models and said proposed digital circuit, the proposed digital circuit being produced by PICO-NPA synthesis;
determining a plurality of modes of circuit operation of said proposed digital circuit;
deriving a sub-circuit corresponding to each of said modes of circuit operation;
performing timing analysis on each of said sub-circuits derived corresponding to each of said modes; and
combining the timing analysis results for said modes to determine an overall maximum circuit delay.
28. The method of claim 27 wherein said proposed digital circuit is received in the form of a circuit graph including components and interconnections between said components.
29. The method of claim 28 wherein said timing models are received for said components and interconnections, said timing models including timing edges and delays.
30. The method of claim 27 wherein said determination of at least one mode of circuit operation is performed by first determining control signals of said digital circuit.
31. The method of claim 30 wherein deriving a sub-circuit for each of said modes is done by:
applying values corresponding to each of said modes to said control signals;
propagating said control signal values through the circuit graph for each of said modes; and
removing disabled timing edges from the circuit graph to create a modified circuit graph for each of said nodes.
32. A system for performing a global timing analysis of a proposed digital circuit comprising:
means for receiving timing models and said proposed digital circuit;
means for determining a plurality of modes of circuit operation of said proposed digital circuit, the proposed digital circuit being a periodic circuit;
means for deriving a sub-circuit corresponding to each of said modes of circuit operation;
means for performing timing analysis on each of said sub-circuits derived corresponding to each of said modes; and
means for combining the timing analysis results for said modes to determine an overall maximum circuit delay.
33. The system of claim 32 wherein said proposed digital circuit is received in the form of a circuit graph.
34. The system of claim 33 wherein said circuit graph includes components and interconnections between said components.
35. The system of claim 32 wherein said timing models are received for components and interconnections of said digital circuit.
36. The system of claim 35 wherein said timing models include timing edges and delays.
37. The system of claim 32 wherein said determination of at least one mode of circuit operation is performed by first determining control signals of said digital circuit.
38. The system of claim 32 wherein said digital circuit is in the form of a circuit graph; said timing models include timing edges and delays; and said determination of at least one mode of circuit operation is performed by first determining control signals of said digital circuit.
39. The system of claim 38 further comprising:
means for applying values corresponding to each of said modes to said control signals;
means for propagating said control signal values through the circuit graph for each of said modes; and
means for removing disabled timing edges from the circuit graph to create a modified circuit graph for each of said nodes.
40. The system of claim 39 further including:
means for disabling timing edges including those timing edges through which no signal propagates in each of said modes.
41. The system of claim 32 wherein said timing analysis is performed using Program Evaluation and Review Technique (PERT).
42. The system of claim 32 wherein said means for determining an overall maximum circuit delay further includes:
means for identifying a mode containing a maximum delay.
43. The system of claim 32 wherein the proposed digital circuit comprises a circuit datapath that is controlled by a finite-state machine based controller.
44. A system for performing a global timing analysis of a proposed digital circuit comprising:
means for receiving timing models and said proposed digital circuit;
means for determining a plurality of modes of circuit operation of said proposed digital circuit, the proposed digital circuit being produced as a result of software pipelining;
means for deriving a sub-circuit corresponding to each of said modes of circuit operation;
means for performing timing analysis on each of said sub-circuits derived corresponding to each of said modes; and
means for combining the timing analysis results for said modes to determine an overall maximum circuit delay.
45. The system of claim 44 wherein the proposed digital circuit is further produced as a result of modulo scheduling.
46. The system of claim 44 wherein the proposed digital circuit is further produced by PICO-NPA synthesis.
47. A computer program product stored on computer readable media comprising computer code for implementing a method of performing a global timing analysis of a proposed digital circuit comprising steps of:
receiving timing models and said proposed digital circuit, the proposed digital circuit being a periodic circuit;
determining a plurality of modes of circuit operation of said proposed digital circuit;
deriving a sub-circuit corresponding to each of said modes of circuit operation;
performing timing analysis on each of said sub-circuits derived corresponding to each of said modes; and
combining the timing analysis results for said modes to determine an overall maximum circuit delay.
48. The computer program product of claim 47 wherein said proposed digital circuit is received in the form of a circuit graph.
49. The computer program product of claim 48 wherein said circuit graph includes components and interconnections between said components.
50. The computer program product of claim 47 wherein said timing models are received for components and interconnections of said digital circuit.
51. The computer program product of claim 50 wherein said timing models include timing edges and delays.
52. The computer program product of claim 47 wherein said determining at least one mode of circuit operation is performed by first determining control signals of said digital circuit.
53. The computer program product of claim 52 wherein said control signals are associated with those signals that control the sensitization of circuit paths with large delay.
54. The computer program product of claim 52 wherein said modes of circuit operation include all possible combinations of control signal values.
55. The computer program product of claim 52 wherein said modes of circuit operation are determined such that in each mode, the control signals that influence the sensitization of those circuit paths with large delay that are sensitized in this mode are assigned a 0 or a 1 value.
56. The computer program product of claim 47 wherein:
said digital circuit is received in the form of a circuit graph;
said timing models include timing edges and delays; and
said determining at least one mode of circuit operation is performed by first determining control signals of said digital circuit.
57. The computer program product of claim 56 wherein deriving a sub-circuit for each of said modes is done by:
applying values corresponding to each of said modes to said control signals;
propagating said control signal values through the circuit graph for each of said modes; and
removing disabled timing edges from the circuit graph to create a modified circuit graph for each of said nodes.
58. The computer program product of claim 57 further including:
disabling timing edges including those timing edges through which no signal propagates in each of said modes.
59. The computer program product of claim 47 wherein said determining an overall maximum circuit delay includes identifying a mode containing a maximum delay.
60. A computer program product stored on computer readable media comprising computer code for implementing a method of performing a global timing analysis of a proposed digital circuit comprising steps of:
receiving timing models and said proposed digital circuit, the proposed digital circuit being produced as a result of software pipelining;
determining a plurality of modes of circuit operation of said proposed digital circuit;
deriving a sub-circuit corresponding to each of said modes of circuit operation;
performing timing analysis on each of said sub-circuits derived corresponding to each of said modes; and
combining the timing analysis results for said modes to determine an overall maximum circuit delay.
61. The computer program product of claim 60 wherein the proposed digital circuit is further produced as a result of modulo scheduling.
62. The computer program product of claim 60 wherein the proposed digital circuit is further produced by PICO-NPA synthesis.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A manufacture method of a pressure sensor, comprising:
providing a first substrate comprising a metal layer, wherein the metal layer is partially exposed on a surface of the first substrate to form a first circuit, a second circuit and a conductive contact;
providing a second substrate having a first surface and a second surface;
mounting the second substrate to the surface of the first substrate in which the first surface of the second substrate faces to the first substrate to define a first chamber, a second chamber and at least one micro channel, wherein the first circuit is configured in the first chamber, the second circuit is configured in the second chamber, and the micro channel extends outward from the first chamber along the border surface of the first substrate and the second substrate;
forming a MEMS element and a reference element on the second substrate, wherein the MEMS element corresponds to the first circuit, and the reference element corresponds to the second circuit;
forming at least a first via and a second via, wherein the first via and the second via penetrate the first surface and the second surface of the second substrate, the first via is connected to the micro channel, and the second via corresponds to the conductive contact;
introducing an anti-sticking material through the first via and the micro channel to form an anti-sticking layer on the inner surface of the first chamber; and
filling a conductive material to the first via and the second via to seal the first via and electrically connect the second substrate and the conductive contact.
2. The manufacture method of the pressure sensor according to claim 1, further comprising:
forming at least one trench on the surface of the first substrate or the first surface of the second substrate to define the micro channel.
3. The manufacture method of the pressure sensor according to claim 1, wherein the micro channel comprises a bent portion bending to horizontal or vertical direction.
4. The manufacture method of the pressure sensor according to claim 1, wherein the micro channel comprises a dam for reducing the inner diameter of the micro channel.
5. The manufacture method of the pressure sensor according to claim 1, further comprising:
forming a notch on a side of the first surface or a side of the second surface of the second substrate for thinning the MEMS element.
6. The manufacture method of the pressure sensor according to claim 1, further comprising:
forming an anti-moving bump on the surface of the first substrate corresponding to the MEMS element.
7. The manufacture method of the pressure sensor according to claim 1, wherein the second via is further connected to the micro channel.
8. The manufacture method of the pressure sensor according to claim 1, wherein the conductive material in the second via and the second substrate form an ohmic contact, wherein the ohmic contact region comprises at least one of silicon, aluminum-copper alloy, titanium nitride and tungsten.
9. The manufacture method of the pressure sensor according to claim 1, wherein the first substrate comprises a complementary metal oxide semiconductor substrate.
10. The manufacture method of the pressure sensor according to claim 1, further comprising:
providing a third substrate, having a notch region and a plurality of bracket structure; and
connecting the third substrate to the surface of the first substrate through the bracket structure to place the second substrate in the notch region.
11. The manufacture method of the pressure sensor according to claim 10, wherein the third substrate comprises a channel configured on the terminal of the bracket structure.
12. A pressure sensor, comprising:
a first substrate, comprising a metal layer, wherein the metal layer is partially exposed on a surface of the first substrate to form a first circuit, a second circuit and a conductive contact;
a second substrate, comprising a first surface, a second surface and at least one contact via, the contact via penetrates the first surface and the second surface of the second substrate and is sealed by a filler, wherein the second substrate faces the surface of the first substrate with the first surface and is electrically connected to the conductive contact, wherein the second substrate comprising:
a MEMS element, corresponding to the first circuit and defining an airtight chamber with the first substrate and the second substrate, wherein the chamber comprises at least one micro channel extending to the contact via; and
a reference element, corresponding to the second circuit and retaining a fixed distance with the second circuit; and
an anti-sticking layer, locating on the inner surface of the chamber.
13. The pressure sensor according to claim 12, wherein the micro channel comprises a bent portion bending to horizontal or vertical direction.
14. The pressure sensor according to claim 12, wherein the micro channel comprises a dam for reducing the inner diameter of the micro channel.
15. The pressure sensor according to claim 12, wherein the micro channel is configured on the first substrate.
16. The pressure sensor according to claim 12, wherein the micro channel is configured on the second substrate.
17. The pressure sensor according to claim 12, wherein the MEMS element comprises a notch configured on side of the first surface or side of the second surface.
18. The pressure sensor according to claim 12, wherein an anti-moving bump is configured on the surface of the first substrate corresponding to the MEMS element.
19. The pressure sensor according to claim 12, wherein the second substrate comprises a conductive via penetrating the first surface and the second surface of the second substrate, wherein the conductive via is electrically connected to the conductive contact and the second substrate through an ohmic contact, and the ohmic contact region comprises at least one of silicon, aluminum-copper alloy, titanium nitride and tungsten.
20. The pressure sensor according to claim 19, wherein the conductive via is integrated to the contact via.
21. The pressure sensor according to claim 12, wherein the first substrate comprises a complementary metal oxide semiconductor substrate.
22. The pressure sensor according to claim 12, further comprising:
a third substrate having a notch region and a plurality of bracket structure, wherein the third substrate is configured above the second substrate and is connected to the first substrate through the bracket structure so that the second substrate is accommodated in the notch region.
23. The pressure sensor according to claim 22, wherein the third substrate comprises a channel configured on the terminal of the bracket structure.