1. A circuit assembly, comprising:
a functional chip including a first logic island and a second logic island; and
a first capacitor configured to be selectively coupled to a first power supply terminal of the first logic island and a second power supply terminal of the second logic island.
2. The circuit assembly of claim 1, where the first capacitor is incorporated within a substrate carrier and is configured to be selectively coupled to the first and second power supply terminals at different times.
3. The circuit assembly of claim 1, further comprising:
a second capacitor configured to be selectively coupled, at different times, to the first power supply terminal of the first logic island and the second power supply terminal of the second logic island.
4. The circuit assembly of claim 3, wherein the first and second capacitors are incorporated within a substrate carrier.
5. The circuit assembly of claim 4, wherein the substrate carrier is a silicon carrier.
6. The circuit assembly of claim 1, further comprising:
a control circuit configured to determine workloads for the first and second logic islands, wherein the control circuit is further configured to provide one or more control signals that cause the first capacitor to be coupled to the first logic island or the second logic island based on the workloads.
7. The circuit assembly of claim 1, wherein the first capacitor is included within a capacitor grid including multiple capacitors that are configured to be selectively coupled, at different times, to the first logic island and the second logic island.
8. The circuit assembly of claim 1, wherein the functional chip is a multi-core processor integrated circuit chip, and wherein the first logic island includes a first processor core and the second logic island includes a second processor core.
9. A method of operating a circuit assembly, comprising:
determining workloads of a first logic island and a second logic island that are included within a functional chip; and
selectively coupling, at different times, a first capacitor to a first power supply terminal of the first logic island and a second power supply terminal of the second logic island based on the workloads.
10. The method of claim 9, wherein the first capacitor is incorporated within a substrate carrier.
11. The method of claim 9, further comprising:
selectively coupling, at different times, a second capacitor to the first power supply terminal of the first logic island and the second power supply terminal of the second logic island based on the workloads.
12. The method of claim 11, wherein the first and second capacitors are incorporated within a substrate carrier.
13. The method of claim 12, wherein the substrate carrier is a silicon carrier.
14. The method of claim 9, wherein the first capacitor is included within a capacitor grid including multiple capacitors that are each configured to be selectively coupled, at different times, to the first logic island and the second logic island.
15. The method of claim 9, wherein the functional chip is a multi-core processor integrated circuit chip, and wherein the first logic island includes a first processor core and the second logic island includes a second processor core.
16. A circuit assembly, comprising:
a functional chip including a first logic island and a second logic island wherein the functional chip is a multi-core processor integrated circuit chip, and wherein the first logic island includes a first processor core and the second logic island includes a second processor core;
a first capacitor configured to be selectively coupled to a first power supply terminal of the first logic island and a second power supply terminal of the second logic island; and
a second capacitor configured to be selectively coupled to the first power supply terminal of the first logic island and the second power supply terminal of the second logic island.
17. The circuit assembly of claim 16, wherein the first and second capacitors are incorporated within a substrate carrier.
18. The circuit assembly of claim 17, wherein the substrate carrier is a silicon carrier.
19. The circuit assembly of claim 18, wherein the first and second capacitors are included within a capacitor grid including multiple capacitors that are configured to be selectively coupled, at different times, to the first logic island and the second logic island.
20. The circuit assembly of claim 16, further comprising:
a third capacitor configured to be selectively coupled to the first power supply terminal of the first logic island and the second power supply terminal of the second logic island.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A transportation device lamp fixture comprising:
a semiconductor light-emitting device;
a circuit board to which the semiconductor light-emitting device is mounted;
a lamp body; and
a front cover that covers an opening of the lamp body,
wherein the semiconductor light-emitting device and the circuit board are housed inside of a lamp chamber formed by the lamp body and the front cover; and
the circuit board is directly attached to an inside surface of an uppermost wall of the front cover that delimits the extent of the lamp chamber or an inside surface of an uppermost wall of the lamp body that delimits the extent of the lamp chamber.
2. The transportation device lamp fixture according to claim 1, further comprising a reflector that reflects light emitted from the semiconductor light-emitting device in front of the lamp fixture, wherein the reflector is attached to one of the front cover and the lamp body, whichever the circuit board is attached to.
3. The transportation device lamp fixture according to claim 2, wherein
the reflector includes a reflective portion for reflecting the light from the semiconductor light-emitting device, and an attaching portion for attaching the reflector to the front cover or the lamp body; and
the circuit board is attached to the front cover or the lamp body via the attaching portion of the reflector.
4. The transportation device lamp fixture according to claim 1, wherein a heat sink is formed on a portion of the upper portion of the front cover or the upper portion of the lamp body, and the circuit board is attached to the heat sink.
5. The transportation device lamp fixture according to claim 1, wherein
the circuit board is attached to the lamp body.
6. The transportation device lamp fixture according to claim 5, wherein
a front surface of a back portion of the lamp body is formed as a reflective portion.
7. The transportation device lamp fixture according to claim 1, wherein the transportation device lamp fixture is mounted to a transportation device that does not have another heat source that is different from the transportation device lamp fixture, and that is located around a predetermined position where the lamp fixture is attached.