1. Circuitry comprising:
a logic circuitry portion; and
a delay circuitry portion including a first transistor;
wherein:
the logic circuitry portion is structured andor electrically connected to: (i) receive a set of input signals including at least a first input signal and a second input signal; and (ii) perform logic functionality on the set of input signals to generate a set of output signal(s); and
the first transistor is structured andor electrically connected to gate the first input signal with the second input signal so that the first input signal is not received by the logic circuitry portion until the second input signal has arrived at the first transistor.
2. The circuitry of claim 1 wherein the logic circuitry portion and delay circuitry portion are integrated into an integrated circuit.
3. The circuitry of claim 2 wherein the integrated circuit is designed so that the first input signal arrives at the first transistor before the second input signal arrives at the first transistor.
4. The circuitry of claim 3 wherein the logic circuitry portion generates the set of output signal(s) by applying at least one of the following types logic functionality to the set of input signals: NAND, XOR, OR, AND, NOR, inverted NAND, inverted XOR, inverted OR, inverted AND, inverted NOR andor complex gates using sub-combinations of the foregoing types of logic functionality.
5. The circuitry of claim 1 wherein the logic circuitry portion generates the set of output signal(s) by applying at least one of the following types logic functionality to the set of input signals: NAND, XOR, OR, AND, NOR, inverted NAND, inverted XOR, inverted OR, inverted AND, inverted NOR andor complex gates using sub-combinations of the foregoing types of logic functionality.
6. Circuitry comprising:
a logic circuitry portion; and
a delay circuitry portion including a first transistor;
wherein:
the logic circuitry portion is structured andor electrically connected to: (i) receive a set of input signal(s); and (ii) perform logic functionality on the set of input signals to generate a set of output signal(s) including at least a first output signal and a second output signal; and
the first transistor is structured andor electrically connected to gate the first output signal with the second output signal so that the first output signal is not output by the logic circuitry portion until the second output signal has arrived at the first transistor.
7. The circuitry of claim 6 wherein the logic circuitry portion and delay circuitry portion are integrated into an integrated circuit.
8. The circuitry of claim 7 wherein the integrated circuit is designed so that the first output signal arrives at the first transistor before the second output signal arrives at the first transistor.
9. The circuitry of claim 8 wherein the logic circuitry portion generates the set of output signal(s) by applying at least one of the following types logic functionality to the set of input signals: NAND, XOR, OR, AND, NOR, inverted NAND, inverted XOR, inverted OR, inverted AND, inverted NOR andor complex gates using sub-combinations of the foregoing types of logic functionality.
10. The circuitry of claim 6 wherein the logic circuitry portion generates the set of output signal(s) by applying at least one of the following types logic functionality to the set of input signals: NAND, XOR, OR, AND, NOR, inverted NAND, inverted XOR, inverted OR, inverted AND, inverted NOR andor complex gates using sub-combinations of the foregoing types of logic functionality.
11. A method of designing an integrated circuit, the method comprising:
defining a set of standard cell(s) including code based representations of a logic circuitry portion, and a delay circuitry portion including a first transistor; and
applying the set of standard cell(s) into an integrated circuit design so that:
the logic circuitry portion is structured andor electrically connected to: (i) receive a set of input signals including at least a first input signal and a second input signal; and (ii) perform logic functionality on the set of input signals to generate a set of output signal(s), and
the first transistor is structured andor electrically connected to gate the first input signal with the second input signal so that the first input signal is not received by the logic circuitry portion until the second input signal has arrived at the first transistor.
12. The method of claim 11 wherein the application of the set of standard cell(s) is performed so that the first input signal arrives at the first transistor before the second input signal arrives at the first transistor.
13. The method of claim 11 wherein the logic circuitry portion generates the set of output signal(s) by applying at least one of the following types logic functionality to the set of input signals: NAND, XOR, OR, AND, NOR, inverted NAND, inverted XOR, inverted OR, inverted AND, inverted NOR andor complex gates using sub-combinations of the foregoing types of logic functionality.
14. The method of claim 11 wherein:
the definition of the set of standard cell(s) is performed so that the delay circuitry and the logic circuitry are both included in a single standard cell.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method, comprising:
enabling state bits of a pseudo least recently used (LRU) scheme of a cache memory device, wherein the state bits comprise root-node bits and lower-node bits for cache lines of the cache memory device, wherein further the lower-node bits are distributed in a plurality of structures of the cache memory device;
disabling bits of a data structure of the cache memory device to reduce power consumption; and
disabling state bits associated with the data structure, wherein the disabling the state bits comprises switching a plurality of the lower-node bits associated with the data structure.
2. The method of claim 1, wherein the enabling the state bits comprise enabling state bits for cache lines arranged into ways and sets.
3. The method of claim 2, wherein the disabling bits of the data array of the cache memory device comprises turning off data bits of a bank of a non-uniform cache access (NUCA) cache of a computing device.
4. The method of claim 1, wherein the root-node bits are stored in a centralized structure, separate from the lower-node bits.
5. The method of claim 1, wherein the root-node bits are distributed with the lower-node bits in the plurality of structures.
6. An apparatus, comprising:
a plurality of decentralized arrays of a cache memory, wherein state bits of a pseudo least recently used (LRU) scheme for the cache memory comprise root-node bits and lower-node bits, wherein further the lower-node bits are stored in the plurality of decentralized arrays; and
a cache controller to turn off the lower-node bits to conserve power.
7. The apparatus of claim 6, further comprising a power management module to turn off portions of the cache memory to conserve power.
8. The apparatus of claim 6, wherein root-node bits are stored in a centralized array of the cache memory, wherein further the centralized array comprises validity bits and coherency bits.
9. The apparatus of claim 8, wherein the cache memory is configured to apply power to the centralized array while some of the decentralized arrays are turned off, wherein further the centralized array comprises higher-node bits.
10. The apparatus of claim 6, wherein root-node bits are stored in the decentralized arrays with the lower-node bits.
11. The apparatus of claim 6, wherein the cache memory comprises a uniform cache access (UCA) cache.
12. The apparatus of claim 6, wherein the cache memory comprises an L3 non-uniform cache access (NUCA) cache module and the cache controller comprises a state machine.
13. The apparatus of claim 12, wherein the cache controller is arranged to turn off banks of the ways and turn off validity bits, coherency bits, and tag bits associated with the ways.
14. The apparatus of claim 12, wherein the cache controller is arranged to turn off banks of the ways and leave at least one of validity bits, coherency bits, and tag bits of the ways enabled, wherein further the root-node bits and lower-node bits comprise bits of a pseudo LRU tree.
15. A system comprising:
a plurality of processors;
a plurality of banks of a cache memory device coupled to the plurality of processors, wherein the cache memory device comprises a plurality of decentralized arrays; and
a cache controller to set state bits of a pseudo least recently used (LRU) scheme for the plurality of banks, wherein the state bits comprise root-node bits and lower-node bits, wherein further the lower-node bits are stored in the plurality of decentralized arrays, wherein further the cache controller is configured to turn off at a portion of the plurality of decentralized arrays to conserve power.
16. The system of claim 15, wherein the cache memory device comprises at least one centralized array to store root-node bits.
17. The system of claim 16, wherein the centralized array remains powered while some of the decentralized arrays are turned off.
18. The system of claim 15, wherein root-node bits are stored in the decentralized arrays with the lower-node bits.
19. The system of claim 18, wherein the decentralized arrays comprise tag information for data arrays.
20. The system of claim 19, wherein the tag information comprises at least one of validity bits and coherency bits, wherein further the cache memory device comprises a non-uniform cache access (NUCA) cache with horizontally-striped ways.