1. An isolated human GBM xenograft identified as TB08-0714 (IDH1R132H homozygous).
2. An isolated human GBM cell line identified as TB08-0714 (IDH1R132H homozygous).
3. An isolated human GBM xenograft identified as TB08-0537 (IDH1R132H heterozygous).
4. An isolated human GBM cell line identified as TB08-0537 (IDH1R132H heterozygous).
5. A method for determining the effect of a test compound on DNA accumulation in an IDH1 gene-defective cell line or xenograft according to any one of the preceding claims, said method comprising:
incubating said IDH1 gene-defective cell line or xenograft in the presence and absence of the test compound;
determining and comparing DNA content in said IDH1 gene-defective cell or xenograft when incubated in the presence and absence of the test compound; and
selecting the test compound which causes DNA accumulation in said IDH1 gene-defective cell or xenograft.
6. The method of claim 5 wherein the method is performed on a pair of isogenic cell lines or xenografts.
7. A method of screening candidate agents for potential as anti-tumor agents in an IDH1 gene-defective cell line or xenograft comprising:
incubating an IDH1 gene-defective cell or xenograft according to any of claims 1-4 in the presence and absence of a candidate agent;
determining and comparing cell viability or apoptosis in the IDH1 gene-defective cell or xenograft in the presence and absence of the candidate agent; and
selecting the candidate agent as a potential anti-tumor agent which reduces cell viability or induces apoptosis in the IDH1 gene-defective cell or xenograft.
8. The method of claim 7 wherein the method is performed on a pair of isogenic cell lines or xenografts.
9. A method for screening the effect of a test compound comprising:
incubating a xenograft according to claim 1 or 3 in the presence and in the absence of the test compound;
determining and comparing morphology of the xenograft in the presence and absence of the test compound; and
selecting the test compound which reduces the tumor morphology or increases the normal morphology.
10. The method of claim 9 wherein the method is performed on a pair of isogenic cell lines or xenografts.
11. The method of claim 9 wherein the step of incubating is performed in vivo in an experimental mammal.
12. The method of claim 5 wherein the IDH1 gene-defective cell line is incubated.
13. The method of claim 7 wherein the IDH1 gene-defective cell line is incubated.
14. The method of claim 5 wherein the IDH1 gene-defective xenograft is incubated.
15. The method of claim 7 wherein the IDH1 gene-defective xenograft is incubated.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method to fabricate a semiconductor device, comprising:
forming a block dielectric layer and a sacrificial layer on a semiconductor substrate; forming trenches by etching the sacrificial layer;
forming sidewall floating gates on lateral faces of the trenches;
forming a block oxide layer on the sidewall floating gates;
forming polysilicon gate electrodes on the resulting structure using a patterning process;
removing the sacrificial layer;
forming sourcedrain areas by implanting impurity ions into the resulting structure; injecting carriers or electric charges into the sidewall floating gates; and
forming sidewall spacers adjacent to the polysilicon gate electrodes and the sidewall floating gates,
wherein the sidewall floating gates have an amount or concentration of electrons or holes under side portions of the polysilicon gate electrodes sufficient to adjust a threshold voltage of the device and form an inversion layer in the substrate under the sidewall floating gates without application of a bias to the sidewall floating gates.
2. The method as defined by claim 1, further comprising forming an insulator layer on the surface of the polysilicon gate electrodes and the sidewall floating gates, after removing the sacrificial layer but before injecting carriers or electric charges into the sidewall floating gates.
3. The method as defined by claim 1, further comprising, before forming the polysilicon gate electrodes, the steps of removing the block dielectric layer from areas in the trenches exposed after forming the sidewall floating gates, and forming a gate oxide layer.
4. The method as defined by claim 1, comprising forming the gate oxide layer and the block oxide layer simultaneously.
5. The method as defined by claim 1, wherein the gate oxide layer and the second block oxide layer are formed by an oxidation process, LPCVD or HDP-CVD.
6. The method as defined by claim 1, wherein the sacrificial layer comprises a material selected from the group consisting of oxides, oxynitrides and nitrides.
7. The method as defined by claim 1, wherein the sidewall floating gates are formed by anisotropic etching.
8. The method as defined by claim 1, wherein the sidewall floating gates comprise heavily doped polysilicon.
9. The method as defined by claim 1, wherein the carriers or electric charges injected into an NMOS transistor comprise holes or negative charges.
10. The method as defined by claim 1, wherein the carriers or electric charges injected into a PMOS transistor comprise electrons or positive charges.
11. The method as defined by claim 10, wherein positive charges of 2.0\xd710\u22126 Ccm3 or more are injected into the sidewall floating gates.
12. The method as defined by claim 1, wherein the carriers or electric charges are injected at a predetermined angle while rotating the semiconductor substrate.
13. The method as defined by claim 1, wherein virtual sourcedrain extension areas are formed under the sidewall floating gates.
14. The method as defined by claim 13, wherein the virtual sourcedrain extension areas is 5 \u212b and less.
15. The method as defined by claim 1, wherein the sourcedrain extension areas are adjusted by controlling the coupling ratio between the block dielectric layer and the block oxide layer.
16. The method as defined by claim 1, wherein a coupling ratio between the block dielectric layer and the block oxide is 0.5 or more.