1. A method of manufacturing semiconductor devices, comprising the steps of:
(a) providing a base material having a first surface, a plurality of device regions formed in the first surface, a plurality of semiconductor chips mounted in the plurality of device regions, respectively, a frame region provided in the first surface and outside the plurality of device regions, a marking region provided in part of the frame region, and first identification information affixed to the marking region,
wherein the first surface has a first side and a second side opposed to the first side;
wherein the frame region has a first region located between the device regions and the first side and a second region other than the first region; and
wherein the marking region is provided in the second region;
(b) after the step (a), sealing the plurality of semiconductor chips with resin and forming a sealing body by clamping the base material using a first metal mold and a second metal mold such that the plurality of semiconductor chips are located inside a cavity provided in the first metal mold and supplying resin into the cavity from the side of the first side of the base material;
(c) after the step (b), reading the first identification information; and
(d) after the step (b), newly affixing a second identification information to the sealing body,
wherein, before the step (b), a dam part of the frame region is formed between the marking region and the plurality of device regions.
2. The method of manufacturing semiconductor devices according to claim 1,
wherein the first metal mold has a gate part in communication with the cavity and a vent part arranged on the opposite side of the gate part through the cavity and in communication with the cavity;
wherein, in the step (b), the resin is supplied from the gate part arranged on the side of the first side of the base material and a gas inside the cavity is discharged from the vent part arranged on the side of the second side of the base material; and
wherein the second region of the frame region is located between the second side and the plurality of device regions.
3. The method of manufacturing semiconductor devices according to claim 1,
wherein the base material is a wiring substrate having an insulating layer, a plurality of wires formed in the insulating layer, and a plurality of terminals formed in the insulating layer.
4. The method of manufacturing semiconductor devices according to claim 1,
wherein the base material is a wiring substrate having a first insulating film formed on the first surface side;
wherein there are formed, on the side of the first side of the base material, a plurality of gate patterns which are metal patterns exposed from the first insulating film and are arranged at a position overlapping a supply port of the resin in the step (b);
wherein, on the side of the second side of the base material, there are formed a plurality of vent patterns which are trench patterns formed in the first insulating film, arranged at a position overlapping an outlet of a gas inside the cavity in the step (b); and
wherein, in an extending direction of the first side and the second side of the base material, a width of each of the plurality of gate patterns is greater than a width of each of the plurality of vent patterns.
5. The method of manufacturing semiconductor devices according to claim 4,
wherein the second region of the frame region is located between the second side and the plurality of device regions.
6. The method of manufacturing semiconductor devices according to claim 5,
wherein the vent patterns are formed in the second region; and
wherein, the marking region is formed between adjacent vent patterns of the plurality of vent patterns.
7. The method of manufacturing semiconductor devices according to claim 1,
wherein each semiconductor chip is electrically coupled with a respective plurality of terminals formed in the base material via a respective plurality of wires, and
wherein, in the step (b), the sealing body is formed by sealing the semiconductor chips and the wires in the cavity with the resin.
8. The method of manufacturing semiconductor devices according to claim 1,
wherein the dam part is a trench pattern formed in the first surface of the base material.
9. The method of manufacturing semiconductor devices according to claim 1,
wherein the base material is a wiring substrate having an insulating layer, a plurality of wirings formed in the insulating layer, a plurality of terminals formed in the insulating layer, and a first insulating film covering the wirings on the side of the first surface, and
wherein the dam part is a trench pattern formed by removing the first insulating film.
10. The method of manufacturing semiconductor devices according to claim 1,
wherein the first surface of the base material is quadrangular;
wherein the dam part has a first portion extending along a first direction in which a side where the marking region is formed extends, a second portion extending along a second direction orthogonal to the first direction, and a third portion opposed to the second portion and extending along the second direction, and
wherein one end of each of the second and third portions is connected to the first portion and the other end extends to the side where the marking region is formed.
11. The method of manufacturing semiconductor devices according to claim 10,
wherein each of the first, second, and third portions extends in a rectilinear manner.
12. The method of manufacturing semiconductor devices according to claim 10,
wherein one or both of the second and third portions extend (s) toward the second direction in a meandering manner.
13. The method of manufacturing semiconductor devices according to claim 1,
wherein, in the step (b), in a state where the base material is arranged between the first metal mold and the second metal mold such that the device regions are positioned inside the cavity, the sealing body is formed by collectively sealing the device regions.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A portion of a memory array, comprising:
a string of two or more non-volatile memory cells;
a first select gate coupled in series with one non-volatile memory cell of the string of two or more non-volatile memory cells; and
a second select gate coupled in series with the first select gate;
wherein a length of the second select gate is greater than a length of the first select gate.
2. The portion of a memory array of claim 1 further comprises:
a third select gate coupled in series with a second non-volatile memory cell of the string of non-volatile memory cells; and
a fourth select gate coupled in series with the third select gate.
3. The portion of a memory array of claim 2, wherein a length of the fourth select gate is greater than a length of the third select gate.
4. The portion of a memory array of claim 2, wherein the length of the second select gate is greater than or equal to a length of the fourth select gate.
5. The portion of a memory array of claim 2, wherein a length of the fourth select gate is greater than or equal to the length of the first select gate.
6. The portion of a memory array of claim 2, wherein lengths of the two or more non-volatile memory cells are selected from the group consisting of lengths less than or equal to the length of the first select gate, the length of the second select gate, a length of the third select gate, and a length of the fourth select gate.
7. The portion of a memory array of claim 1 further comprises a bit line coupled to the second select gate.
8. A portion of a NAND architecture memory array, comprising:
two or more series-coupled non-volatile memory cells;
a first select gate coupled in series with one of the of the series-coupled non-volatile memory cells; and
a second select gate coupled in series with the first select gate;
wherein a length of the second select gate is greater than a length of the first select gate.
9. The portion of the NAND architecture memory array of claim 8 further comprises:
a third select gate coupled in series with a second one of the series-coupled non-volatile memory cells; and
a fourth select gate coupled in series with the third select gate.
10. The portion of the NAND architecture memory array of claim 9, wherein a length of the fourth select gate is greater than a length of the third select gate.
11. The portion of the NAND architecture memory array of claim 9, wherein the length of the second select gate is greater than or equal to a length of the fourth select gate.
12. The portion of the NAND architecture memory array of claim 9, wherein a length of the fourth select gate is greater than or equal to the length of the first select gate.
13. The portion of the NAND architecture memory array of claim 9, wherein lengths of the two or more non-volatile memory cells are selected from the group consisting of lengths less than or equal to the length of the first select gate, the length of the second select gate, a length of the third select gate, and a length of the fourth select gate.
14. A portion of a memory array, comprising:
a string of two or more non-volatile memory cells;
a first select gate coupled in series with a first non-volatile memory cell of the string of two or more non-volatile memory cells;
a second select gate coupled in series with the first select gate;
a third select gate coupled in series with a last non-volatile memory cell of the string of two or more non-volatile memory cells; and
a fourth select gate coupled in series with the third select gate;
wherein a length of the second select gate is greater than a length of the first select gate; and
wherein a length of the fourth select gate is greater than a length of the third select gate.
15. The portion of a memory array of claim 14, wherein the length of the second select gate is greater than or equal to the length of the fourth select gate.
16. The portion of a memory array of claim 14, wherein the length of the fourth select gate is greater than or equal to the length of the first select gate.
17. The portion of a memory array of claim 14, wherein lengths of the two or more non-volatile memory cells are selected from the group consisting of lengths less than or equal to the length of the first select gate, the length of the second select gate, the length of the third select gate, and the length of the fourth select gate.
18. The portion of a memory array of claim 14 further comprises a bit line coupled to the second select gate.
19. The portion of a memory array of claim 14 further comprises a source line coupled to the fourth select gate.
20. A portion of a NAND architecture memory array, comprising:
two or more series-coupled non-volatile memory cells;
a first select gate coupled in series with a first non-volatile memory cell of the series-coupled non-volatile memory cells;
a second select gate coupled in series with the first select gate;
a third select gate coupled in series with a last non-volatile memory cell of the series-coupled non-volatile memory cells; and
a fourth select gate coupled in series with the third select gate;
wherein a length of the second select gate is greater than a length of the first select gate; and
wherein a length of the fourth select gate is greater than a length of the third select gate.
21. The portion of the NAND architecture memory array of claim 20, wherein the length of the second select gate is greater than or equal to the length of the fourth select gate.
22. The portion of the NAND architecture memory array of claim 20, wherein the length of the fourth select gate is greater than or equal to a length of the first select gate.
23. The portion of the NAND architecture memory array of claim 20, wherein lengths of the two or more non-volatile memory cells are selected from the group consisting of lengths less than or equal to the length of the first select gate, the length of the second select gate, the length of the third select gate, and the length of the fourth select gate.
24. A portion of a NAND architecture memory array, comprising:
a first select gate having a first sourcedrain region and a second sourcedrain region;
a second select gate having a first sourcedrain region and a second sourcedrain region, wherein the first sourcedrain region of the second select gate is coupled to the second sourcedrain region of the first select gate; and
a plurality of series-coupled non-volatile memory cells, wherein an end one of the series-coupled non-volatile memory cells has a first sourcedrain region and a second sourcedrain region and wherein the first sourcedrain region of the end one of the series-coupled non-volatile memory cells is coupled to the second sourcedrain region of the second select gate;
wherein a length of the first select gate is greater than a length of the second select gate.
25. The portion of the NAND architecture memory array of claim 24, wherein a length of each of the non-volatile memory cells is selected from the group consisting of lengths less than or equal to the length of the first select gate and the length of the second select gate.
26. The portion of the NAND architecture memory array of claim 24 further comprises a bit line coupled to the first sourcedrain region of the first select gate.
27. A portion of a NAND architecture memory array, comprising:
a first select gate having a first sourcedrain region and a second sourcedrain region;
a second select gate having a first sourcedrain region and a second sourcedrain region, wherein the first sourcedrain region of the second select gate is coupled to the second sourcedrain region of the first select gate;
a third select gate having a first sourcedrain region and a second sourcedrain region;
a fourth select gate having a first sourcedrain region and a second sourcedrain region, wherein the first sourcedrain region of the fourth select gate is coupled to the second sourcedrain region of the third select gate; and
a string of series-coupled non-volatile memory cells, wherein a first non-volatile memory cell located at a first end of the string of series-coupled non-volatile memory cells has a first sourcedrain region and a second sourcedrain region, wherein the first sourcedrain region of the first non-volatile memory cell is coupled to the second sourcedrain region of the second select gate, wherein a second non-volatile memory cell located at a second end of the string of series-coupled non-volatile memory cells opposite the first end has a first sourcedrain region and a second sourcedrain region, wherein the second sourcedrain region of the second non-volatile memory cell is coupled to the first sourcedrain region of the third select gate;
wherein a length of the first select gate is greater than a length of the second select gate; and
wherein a length of the fourth select gate is greater than a length of the third select gate.
28. The portion of the NAND architecture memory array of claim 27, wherein the length of the first select gate is greater than or equal to the length of the fourth select gate.
29. The portion of the NAND architecture memory array of claim 27, wherein the length of the fourth select gate is greater than or equal to the length of the second select gate.
30. The portion of the NAND architecture memory array of claim 27, wherein lengths of each of the non-volatile memory cells are selected from the group consisting of lengths less than or equal to the length of the first select gate, the length of the second select gate, the length of the third select gate, and the length of the fourth select gate.
31. The portion of the NAND architecture memory array of claim 27 further comprises a bit line coupled to the first sourcedrain region of the first select gate.
32. The portion of the NAND architecture memory array of claim 31 further comprises a source line coupled to the second sourcedrain region of the fourth select gate.
33. A memory device, comprising:
an array of non-volatile memory cells; and
circuitry for control andor access of the array of non-volatile memory cells;
wherein the array of non-volatile memory cells comprises:
one or more strings of two or more series-coupled non-volatile memory cells;
a first select gate coupled in series with one non-volatile memory cell of each of the one or more strings of two or more series-coupled non-volatile memory cells; and
a second select gate coupled in series with the first select gate;
wherein a length of the second select gate is greater than a length of the first select gate.
34. A memory device, comprising:
an array of non-volatile memory cells; and
circuitry for control andor access of the array of non-volatile memory cells;
wherein the array of non-volatile memory cells comprises:
one or more strings of two or more series-coupled non-volatile memory cells;
a first select gate coupled in series with a first non-volatile memory cell of each of the one or more strings of two or more series-coupled non-volatile memory cells;
a second select gate coupled in series with the first select gate;
a third select gate coupled in series with a last non-volatile memory cell of each of the one or more strings of two or more series-coupled non-volatile memory cells; and
a fourth select gate coupled in series with the third select gate;
wherein a length of the second select gate is greater than a length of the first select gate; and
wherein a length of the fourth select gate is greater than a length of the third select gate.
35. A memory device, comprising:
an array of non-volatile memory cells; and
circuitry for control andor access of the array of non-volatile memory cells;
wherein the array of non-volatile memory cells comprises:
at least one string of two or more series-coupled non-volatile memory cells, wherein an end one of the series-coupled non-volatile memory cells of the at least one string of series-coupled non-volatile memory cells has a first sourcedrain region and a second sourcedrain region;
a first select gate having a first sourcedrain region and a second sourcedrain region; and
a second select gate having a first sourcedrain region and a second sourcedrain region, wherein the first sourcedrain region of the second select gate is coupled to the second sourcedrain region of the first select gate, and wherein the second sourcedrain region of the second select gate is coupled to the first sourcedrain region of the end one of the series-coupled non-volatile memory cells of the at least one string of series-coupled non-volatile memory cells;
wherein a length of the first select gate is greater than a length of the second select gate.
36. A memory device, comprising:
an array of non-volatile memory cells; and
circuitry for control andor access of the array of non-volatile memory cells;
wherein the array of non-volatile memory cells comprises:
at least one string of series-coupled non-volatile memory cells, wherein a first non-volatile memory cell located at a first end of the at least one string of series-coupled non-volatile memory cells has a first sourcedrain region and a second sourcedrain region, and wherein a second non-volatile memory cell located at a second end of the at least one string of series-coupled non-volatile memory cells opposite the first end has a first sourcedrain region and a second sourcedrain region;
a first select gate having a first sourcedrain region and a second sourcedrain region;
a second select gate having a first sourcedrain region and a second sourcedrain region, wherein the first sourcedrain region of the second select gate is coupled to the second sourcedrain region of the first select gate, and wherein the second sourcedrain region of the second select gate is coupled to the first sourcedrain region of the first non-volatile memory cell of the at least one string of series-coupled non-volatile memory cells;
a third select gate having a first sourcedrain region and a second sourcedrain region, wherein the first sourcedrain region of the third select gate is coupled to the second sourcedrain region of the second non-volatile memory cell of the at least one string of series-coupled non-volatile memory cells; and
a fourth select gate having a first sourcedrain region and a second sourcedrain region, wherein the first sourcedrain region of the fourth select gate is coupled to the second sourcedrain region of the third select gate;
wherein a length of the first select gate is greater than a length of the second select gate; and
wherein a length of the fourth select gate is greater than a length of the third select gate.
37. A memory device, comprising:
an array of non-volatile memory cells; and
circuitry for control andor access of the array of non-volatile memory cells;
wherein the array of non-volatile memory cells comprises:
at least one string of series-coupled non-volatile memory cells, wherein a first non-volatile memory cell located at a first end of the at least one string of series-coupled non-volatile memory cells has a first sourcedrain region and a second sourcedrain region, and wherein a second non-volatile memory cell located at a second end of the at least one string of series-coupled non-volatile memory cells opposite the first end has a first sourcedrain region and a second sourcedrain region;
a first select gate having a first sourcedrain region and a second sourcedrain region;
a second select gate having a first sourcedrain region and a second sourcedrain region, wherein the first sourcedrain region of the second select gate is coupled to the second sourcedrain region of the first select gate, and wherein the second sourcedrain region of the second select gate is coupled to the first sourcedrain region of the first non-volatile memory cell of the at least one string of series-coupled non-volatile memory cells;
a third select gate having a first sourcedrain region and a second sourcedrain region, wherein the first sourcedrain region of the third select gate is coupled to the second sourcedrain region of the second non-volatile memory cell of the at least one string of series-coupled non-volatile memory cells;
a fourth select gate having a first sourcedrain region and a second sourcedrain region, wherein the first sourcedrain region of the fourth select gate is coupled to the second sourcedrain region of the third select gate;
a bit line coupled to the first sourcedrain region of the first select gate; and
a source line coupled to the second sourcedrain region of the fourth select gate;
wherein a length of the first select gate is greater than a length of the second select gate; and
wherein a length of the fourth select gate is greater than a length of the third select gate.
38. A memory module, comprising:
a plurality of contacts; and
two or more memory devices, each having access lines selectively coupled to the plurality of contacts;
wherein at least one of the memory devices comprises:
an array of non-volatile memory cells; and
circuitry for control andor access of the array of non-volatile memory cells;
wherein the array of non-volatile memory cells comprises:
one or more strings of two or more series-coupled non-volatile memory cells;
a first select gate coupled in series with one non-volatile memory cell of each of the one or more strings of two or more series-coupled non-volatile memory cells; and
a second select gate coupled in series with the first select gate;
wherein a length of the second select gate is greater than a length of the first select gate.
39. A memory module, comprising:
a plurality of contacts; and
two or more memory devices, each having access lines selectively coupled to the plurality of contacts;
wherein at least one of the memory devices comprises:
an array of non-volatile memory cells; and
circuitry for control andor access of the array of non-volatile memory cells;
wherein the array of non-volatile memory cells comprises:
one or more strings of two or more series-coupled non-volatile memory cells;
a first select gate coupled in series with a first non-volatile memory cell of each of the one or more strings of two or more series-coupled non-volatile memory cells;
a second select gate coupled in series with the first select gate;
a third select gate coupled in series with a last non-volatile memory cell of each of the one or more strings of two or more series-coupled non-volatile memory cells; and
a fourth select gate coupled in series with the third select gate;
wherein a length of the second select gate is greater than a length of the first select gate; and
wherein a length of the fourth select gate is greater than a length of the third select gate.
40. A memory module, comprising:
a plurality of contacts; and
two or more memory devices, each having access lines selectively coupled to the plurality of contacts;
wherein at least one of the memory devices comprises:
an array of non-volatile memory cells; and
circuitry for control andor access of the array of non-volatile memory cells;
wherein the array of non-volatile memory cells comprises:
at least one string of two or more series-coupled non-volatile memory cells, wherein an end one of the series-coupled non-volatile memory cells of the at least one string of series-coupled non-volatile memory cells has a first sourcedrain region and a second sourcedrain region;
a first select gate having a first sourcedrain region and a second sourcedrain region; and
a second select gate having a first sourcedrain region and a second sourcedrain region, wherein the first sourcedrain region of the second select gate is coupled to the second sourcedrain region of the first select gate, and wherein the second sourcedrain region of the second select gate is coupled to the first sourcedrain region of the end one of the series-coupled non-volatile memory cells of the at least one string of series-coupled non-volatile memory cells;
wherein a length of the first select gate is greater than a length of the second select gate.
41. A memory module, comprising:
a plurality of contacts; and
two or more memory devices, each having access lines selectively coupled to the plurality of contacts;
wherein at least one of the memory devices comprises:
an array of non-volatile memory cells; and
circuitry for control andor access of the array of non-volatile memory cells;
wherein the array of non-volatile memory cells comprises:
at least one string of series-coupled non-volatile memory cells, wherein a first non-volatile memory cell located at a first end of the at least one string of series-coupled non-volatile memory cells has a first sourcedrain region and a second sourcedrain region, and wherein a second non-volatile memory cell located at a second end of the at least one string of series-coupled non-volatile memory cells opposite the first end has a first sourcedrain region and a second sourcedrain region;
a first select gate having a first sourcedrain region and a second sourcedrain region;
a second select gate having a first sourcedrain region and a second sourcedrain region, wherein the first sourcedrain region of the second select gate is coupled to the second sourcedrain region of the first select gate, and wherein the second sourcedrain region of the second select gate is coupled to the first sourcedrain region of the first non-volatile memory cell of the at least one string of series-coupled non-volatile memory cells;
a third select gate having a first sourcedrain region and a second sourcedrain region, wherein the first sourcedrain region of the third select gate is coupled to the second sourcedrain region of the second non-volatile memory cell of the at least one string of series-coupled non-volatile memory cells; and
a fourth select gate having a first sourcedrain region and a second sourcedrain region, wherein the first sourcedrain region of the fourth select gate is coupled to the second sourcedrain region of the third select gate;
wherein a length of the first select gate is greater than a length of the second select gate; and
wherein a length of the fourth select gate is greater than a length of the third select gate.
42. A memory module, comprising:
a plurality of contacts; and
two or more memory devices, each having access lines selectively coupled to the plurality of contacts;
wherein at least one of the memory devices comprises:
an array of non-volatile memory cells; and
circuitry for control andor access of the array of non-volatile memory cells;
wherein the array of non-volatile memory cells comprises:
at least one string of series-coupled non-volatile memory cells, wherein a first non-volatile memory cell located at a first end of the at least one string of series-coupled non-volatile memory cells has a first sourcedrain region and a second sourcedrain region, and wherein a second non-volatile memory cell located at a second end of the at least one string of series-coupled non-volatile memory cells opposite the first end has a first sourcedrain region and a second sourcedrain region;
a first select gate having a first sourcedrain region and a second sourcedrain region;
a second select gate having a first sourcedrain region and a second sourcedrain region, wherein the first sourcedrain region of the second select gate is coupled to the second sourcedrain region of the first select gate, and wherein the second sourcedrain region of the second select gate is coupled to the first sourcedrain region of the first non-volatile memory cell of the at least one string of series-coupled non-volatile memory cells;
a third select gate having a first sourcedrain region and a second sourcedrain region, wherein the first sourcedrain region of the third select gate is coupled to the second sourcedrain region of the second non-volatile memory cell of the at least one string of series-coupled non-volatile memory cells;
a fourth select gate having a first sourcedrain region and a second sourcedrain region, wherein the first sourcedrain region of the fourth select gate is coupled to the second sourcedrain region of the third select gate;
a bit line coupled to the first sourcedrain region of the first select gate; and
a source line coupled to the second sourcedrain region of the fourth select gate;
wherein a length of the first select gate is greater than a length of the second select gate; and
wherein a length of the fourth select gate is greater than a length of the third select gate.
43. A memory module, comprising:
a housing having a plurality of contacts; and
one or more memory devices enclosed in the housing and selectively coupled to the plurality of contacts;
wherein at least one of the memory devices comprises:
an array of non-volatile memory cells; and
circuitry for control andor access of the array of non-volatile memory cells;
wherein the array of non-volatile memory cells comprises:
one or more strings of two or more series-coupled non-volatile memory cells;
a first select gate coupled in series with one non-volatile memory cell of each of the one or more strings of two or more series-coupled non-volatile memory cells; and
a second select gate coupled in series with the first select gate;
wherein a length of the second select gate is greater than a length of the first select gate.
44. A memory module, comprising:
a housing having a plurality of contacts; and
one or more memory devices enclosed in the housing and selectively coupled to the plurality of contacts;
wherein at least one of the memory devices comprises:
an array of non-volatile memory cells; and
circuitry for control andor access of the array of non-volatile memory cells;
wherein the array of non-volatile memory cells comprises:
one or more strings of two or more series-coupled non-volatile memory cells;
a first select gate coupled in series with a first non-volatile memory cell of each of the one or more strings of two or more series-coupled non-volatile memory cells;
a second select gate coupled in series with the first select gate;
a third select gate coupled in series with a last non-volatile memory cell of each of the one or more strings of two or more series-coupled non-volatile memory cells; and
a fourth select gate coupled in series with the third select gate;
wherein a length of the second select gate is greater than a length of the first select gate; and
wherein a length of the fourth select gate is greater than a length of the third select gate.
45. A memory module, comprising:
a housing having a plurality of contacts; and
one or more memory devices enclosed in the housing and selectively coupled to the plurality of contacts;
wherein at least one of the memory devices comprises:
an array of non-volatile memory cells; and
circuitry for control andor access of the array of non-volatile memory cells;
wherein the array of non-volatile memory cells comprises:
at least one string of two or more series-coupled non-volatile memory cells, wherein an end one of the series-coupled non-volatile memory cells of the at least one string of series-coupled non-volatile memory cells has a first sourcedrain region and a second sourcedrain region;
a first select gate having a first sourcedrain region and a second sourcedrain region; and
a second select gate having a first sourcedrain region and a second sourcedrain region, wherein the first sourcedrain region of the second select gate is coupled to the second sourcedrain region of the first select gate, and wherein the second sourcedrain region of the second select gate is coupled to the first sourcedrain region of the end one of the series-coupled non-volatile memory cells of the at least one string of series-coupled non-volatile memory cells;
wherein a length of the first select gate is greater than a length of the second select gate.
46. A memory module, comprising:
a housing having a plurality of contacts; and
one or more memory devices enclosed in the housing and selectively coupled to the plurality of contacts;
wherein at least one of the memory devices comprises:
an array of non-volatile memory cells; and
circuitry for control andor access of the array of non-volatile memory cells;
wherein the array of non-volatile memory cells comprises:
at least one string of series-coupled non-volatile memory cells, wherein a first non-volatile memory cell located at a first end of the at least one string of series-coupled non-volatile memory cells has a first sourcedrain region and a second sourcedrain region, and wherein a second non-volatile memory cell located at a second end of the at least one string of series-coupled non-volatile memory cells opposite the first end has a first sourcedrain region and a second sourcedrain region;
a first select gate having a first sourcedrain region and a second sourcedrain region;
a second select gate having a first sourcedrain region and a second sourcedrain region, wherein the first sourcedrain region of the second select gate is coupled to the second sourcedrain region of the first select gate, and wherein the second sourcedrain region of the second select gate is coupled to the first sourcedrain region of the first non-volatile memory cell of the at least one string of series-coupled non-volatile memory cells;
a third select gate having a first sourcedrain region and a second sourcedrain region, wherein the first sourcedrain region of the third select gate is coupled to the second sourcedrain region of the second non-volatile memory cell of the at least one string of series-coupled non-volatile memory cells; and
a fourth select gate having a first sourcedrain region and a second sourcedrain region, wherein the first sourcedrain region of the fourth select gate is coupled to the second sourcedrain region of the third select gate;
wherein a length of the first select gate is greater than a length of the second select gate; and
wherein a length of the fourth select gate is greater than a length of the third select gate.
47. A memory module, comprising:
a housing having a plurality of contacts; and
one or more memory devices enclosed in the housing and selectively coupled to the plurality of contacts;
wherein at least one of the memory devices comprises:
an array of non-volatile memory cells; and
circuitry for control andor access of the array of non-volatile memory cells;
wherein the array of non-volatile memory cells comprises:
at least one string of series-coupled non-volatile memory cells, wherein a first non-volatile memory cell located at a first end of the at least one string of series-coupled non-volatile memory cells has a first sourcedrain region and a second sourcedrain region, and wherein a second non-volatile memory cell located at a second end of the at least one string of series-coupled non-volatile memory cells opposite the first end has a first sourcedrain region and a second sourcedrain region;
a first select gate having a first sourcedrain region and a second sourcedrain region;
a second select gate having a first sourcedrain region and a second sourcedrain region, wherein the first sourcedrain region of the second select gate is coupled to the second sourcedrain region of the first select gate, and wherein the second sourcedrain region of the second select gate is coupled to the first sourcedrain region of the first non-volatile memory cell of the at least one string of series-coupled non-volatile memory cells;
a third select gate having a first sourcedrain region and a second sourcedrain region, wherein the first sourcedrain region of the third select gate is coupled to the second sourcedrain region of the second non-volatile memory cell of the at least one string of series-coupled non-volatile memory cells;
a fourth select gate having a first sourcedrain region and a second sourcedrain region, wherein the first sourcedrain region of the fourth select gate is coupled to the second sourcedrain region of the third select gate;
a bit line coupled to the first sourcedrain region of the first select gate; and
a source line coupled to the second sourcedrain region of the fourth select gate;
wherein a length of the first select gate is greater than a length of the second select gate; and
wherein a length of the fourth select gate is greater than a length of the third select gate.
48. An electronic system, comprising:
a processor; and
one or more memory devices coupled to the processor, wherein at least one of the memory devices comprises:
an array of non-volatile memory cells; and
circuitry for control andor access of the array of non-volatile memory cells;
wherein the array of non-volatile memory cells comprises:
one or more strings of two or more series-coupled non-volatile memory cells;
a first select gate coupled in series with one non-volatile memory cell of each of the one or more strings of two or more series-coupled non-volatile memory cells; and
a second select gate coupled in series with the first select gate;
wherein a length of the second select gate is greater than a length of the first select gate.
49. An electronic system, comprising:
a processor; and
one or more memory devices coupled to the processor, wherein at least one of the memory devices comprises:
an array of non-volatile memory cells; and
circuitry for control andor access of the array of non-volatile memory cells;
wherein the array of non-volatile memory cells comprises:
one or more strings of two or more series-coupled non-volatile memory cells;
a first select gate coupled in series with a first non-volatile memory cell of each of the one or more strings of two or more series-coupled non-volatile memory cells;
a second select gate coupled in series with the first select gate;
a third select gate coupled in series with a last non-volatile memory cell of each of the one or more strings of two or more series-coupled non-volatile memory cells; and
a fourth select gate coupled in series with the third select gate;
wherein a length of the second select gate is greater than a length of the first select gate; and
wherein a length of the fourth select gate is greater than a length of the third select gate.
50. An electronic system, comprising:
a processor; and
one or more memory devices coupled to the processor, wherein at least one of the memory devices comprises:
an array of non-volatile memory cells; and
circuitry for control andor access of the array of non-volatile memory cells;
wherein the array of non-volatile memory cells comprises:
at least one string of two or more series-coupled non-volatile memory cells, wherein an end one of the series-coupled non-volatile memory cells of the at least one string of series-coupled non-volatile memory cells has a first sourcedrain region and a second sourcedrain region;
a first select gate having a first sourcedrain region and a second sourcedrain region; and
a second select gate having a first sourcedrain region and a second sourcedrain region, wherein the first sourcedrain region of the second select gate is coupled to the second sourcedrain region of the first select gate, and wherein the second sourcedrain region of the second select gate is coupled to the first sourcedrain region of the end one of the series-coupled non-volatile memory cells of the at least one string of series-coupled non-volatile memory cells;
wherein a length of the first select gate is greater than a length of the second select gate.
51. An electronic system, comprising:
a processor; and
one or more memory devices coupled to the processor, wherein at least one of the memory devices comprises:
an array of non-volatile memory cells; and
circuitry for control andor access of the array of non-volatile memory cells;
wherein the array of non-volatile memory cells comprises:
at least one string of series-coupled non-volatile memory cells, wherein a first non-volatile memory cell located at a first end of the at least one string of series-coupled non-volatile memory cells has a first sourcedrain region and a second sourcedrain region, and wherein a second non-volatile memory cell located at a second end of the at least one string of series-coupled non-volatile memory cells opposite the first end has a first sourcedrain region and a second sourcedrain region;
a first select gate having a first sourcedrain region and a second sourcedrain region;
a second select gate having a first sourcedrain region and a second sourcedrain region, wherein the first sourcedrain region of the second select gate is coupled to the second sourcedrain region of the first select gate, and wherein the second sourcedrain region of the second select gate is coupled to the first sourcedrain region of the first non-volatile memory cell of the at least one string of series-coupled non-volatile memory cells;
a third select gate having a first sourcedrain region and a second sourcedrain region, wherein the first sourcedrain region of the third select gate is coupled to the second sourcedrain region of the second non-volatile memory cell of the at least one string of series-coupled non-volatile memory cells; and
a fourth select gate having a first sourcedrain region and a second sourcedrain region, wherein the first sourcedrain region of the fourth select gate is coupled to the second sourcedrain region of the third select gate;
wherein a length of the first select gate is greater than a length of the second select gate; and
wherein a length of the fourth select gate is greater than a length of the third select gate.
52. An electronic system, comprising:
a processor; and
one or more memory devices coupled to the processor, wherein at least one of the memory devices comprises:
an array of non-volatile memory cells; and
circuitry for control andor access of the array of non-volatile memory cells;
wherein the array of non-volatile memory cells comprises:
at least one string of series-coupled non-volatile memory cells, wherein a first non-volatile memory cell located at a first end of the at least one string of series-coupled non-volatile memory cells has a first sourcedrain region and a second sourcedrain region, and wherein a second non-volatile memory cell located at a second end of the at least one string of series-coupled non-volatile memory cells opposite the first end has a first sourcedrain region and a second sourcedrain region;
a first select gate having a first sourcedrain region and a second sourcedrain region;
a second select gate having a first sourcedrain region and a second sourcedrain region, wherein the first sourcedrain region of the second select gate is coupled to the second sourcedrain region of the first select gate, and wherein the second sourcedrain region of the second select gate is coupled to the first sourcedrain region of the first non-volatile memory cell of the at least one string of series-coupled non-volatile memory cells;
a third select gate having a first sourcedrain region and a second sourcedrain region, wherein the first sourcedrain region of the third select gate is coupled to the second sourcedrain region of the second non-volatile memory cell of the at least one string of series-coupled non-volatile memory cells;
a fourth select gate having a first sourcedrain region and a second sourcedrain region, wherein the first sourcedrain region of the fourth select gate is coupled to the second sourcedrain region of the third select gate;
a bit line coupled to the first sourcedrain region of the first select gate; and
a source line coupled to the second sourcedrain region of the fourth select gate;
wherein a length of the first select gate is greater than a length of the second select gate; and
wherein a length of the fourth select gate is greater than a length of the third select gate.