1. A memory cell, comprising:
an access device comprising:
a single crystalline semiconductor fin on a substrate extending in a first direction, and separated by insulators from laterally adjacent single crystalline semiconductor fins;
a first doped semiconductor region having a first conductivity type in the single crystalline conductive fin; and
a polycrystalline member on top of the first doped semiconductor region, the polycrystalline member including a second doped semiconductor region having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn-junction therebetween;
wherein the doping concentration of the second doped semiconductor region is in a range about 10 to about 1000 times higher than the doping concentration of the first doped semiconductor region;
an electrode electrically connected to the polycrystalline member;
a memory element contacting the electrode;
a conductive line extending in a second direction, over and electrically connected to the memory element; and
a peripheral area on the substrate including a peripheral circuit single crystal semiconductor region which is part of a single crystal semiconductor body or layer that includes the single crystalline semiconductor fin, the peripheral circuit single crystal semiconductor region including a channel of an FET, a gate dielectric material on the channel and a gate, and wherein the polycrystalline member contacts the first doped semiconductor region without intervening gate dielectric material.
2. The memory cell of claim 1, the memory element comprising a programmable resistance memory material.
3. The memory cell of claim 1 wherein the first doped semiconductor region comprises a P-type semiconductor and the second doped semiconductor region comprises a N-type polycrystalline semiconductor.
4. The memory cell of claim 1 wherein the first doped semiconductor region comprises a N-type semiconductor and the second doped semiconductor region comprises a P-type polycrystalline semiconductor.
5. The memory cell of claim 1, further comprising an electrically conductive cap on the second doped semiconductor region.
6. The memory cell of claim 5 wherein the cap comprises a silicide.
7. The memory cell of claim 1 wherein the polycrystalline member has sides vertically self-aligned with sides of the single-crystalline fin.
8. The memory cell of claim 1 wherein the polycrystalline member and transistor gates in a peripheral circuit region comprise respective patterned polysilicon bodies in a single polysilicon layer.
9. The memory cell of claim 1, further comprising a barrier between the first doped semiconductor region and the second doped semiconductor region.
10. The memory cell of claim 9 wherein the barrier comprises SiO2.
11. The memory cell of claim 9 wherein the barrier comprises SiNxOy.
12. The memory cell of claim 9 wherein the barrier has a thickness in a range about 5 to 25 Angstroms.
13. The memory device of claim 1, wherein the first doped semiconductor region in the doped, single crystal semiconductor fin has a first width in the first direction, and the polysilicon member has a second width in the first direction, and the first width is greater than the second width.
14. A memory device on an integrated circuit substrate, comprising
a plurality of doped, single crystal semiconductor fins protruding from the substrate, having a first conductivity type and extending in a first direction;
a plurality of access lines extending in a second direction overlying and spaced away from the plurality of doped, single crystal semiconductor fins;
a plurality of first doped semiconductor regions having the first conductivity type in the plurality of doped, single crystal semiconductor fins,
a plurality of polysilicon members, the polysilicon members on corresponding first doped semiconductor regions in the plurality of doped, single crystal semiconductor fins, the polysilicon members each including a second doped semiconductor region having a second conductivity type opposite the first conductivity type, the first and second doped semiconductor regions defining a pn-junction therebetween, wherein the doping concentration of the second doped semiconductor region is in a range about 10 to about 1000 times higher than the doping concentration of the first doped semiconductor region, and
electrically conductive caps on the plurality of polysilicon members; and
elements of a memory material in electrical communication with the conductive cap, the elements of memory material underlying and in electrical communication with a corresponding one of the plurality of second access lines; and
a peripheral area on the substrate including a peripheral circuit single crystal semiconductor region which is part of a single crystal semiconductor body or layer that includes the plurality of doped, single crystal semiconductor fins, the peripheral circuit single crystal semiconductor region including a channel of an FET, a gate dielectric material on the channel and a gate, and wherein the plurality of polysilicon members contact the plurality of first doped semiconductor regions without intervening gate dielectric material.
15. The memory device of claim 14, including a peripheral area including a peripheral circuit single crystal semiconductor body on or in the substrate, and providing a channel of an FET, a gate dielectric material on the channel and a gate, and wherein the second doped semiconductor region contacts the first doped semiconductor region without intervening gate dielectric material, and wherein the plurality of polysilicon members and the gate in the peripheral area comprise respective patterned polysilicon bodies in a single polysilicon layer.
16. The memory device of claim 14 wherein the doped, single crystal semiconductor fins comprise P-type semiconductor and the second doped semiconductor regions comprise N-type polycrystalline semiconductor, and the cap comprises a silicide.
17. The memory device of claim 16 wherein the doped, single crystal semiconductor fins comprise a conductively-doped P-type semiconductor in a doped, single crystal semiconductor body.
18. The memory device of claim 16 wherein the doped, single crystal semiconductor fins comprise conductively-doped P-type semiconductor in a doped, single crystal semiconductor body, and including a conductive cap layer on surface portions of the conductively-doped P-type semiconductor between the polysilicon members.
19. The memory device of claim 14 wherein the doped, single crystal semiconductor fins comprise N-type semiconductor in a doped, single crystal semiconductor body and the second doped semiconductor regions comprise P-type polycrystalline semiconductor.
20. The memory device of claim 19 wherein the doped, single crystal semiconductor fins comprise conductively-doped N-type semiconductor in the doped, single crystal semiconductor body.
21. The memory device of claim 19 wherein the doped, single crystal semiconductor fins comprise conductively-doped N-type semiconductor in the doped, single crystal semiconductor body, and including a conductive cap layer on surface portions of the conductively-doped N-type semiconductor between the polysilicon members.
22. The memory device of claim 14 further comprising a bottom electrode between the cap and the elements of a memory material.
23. The memory device of claim 14 wherein the polycrystalline members have sides vertically self-aligned with sides of the single-crystalline fins.
24. The memory device of claim 14 wherein the polycrystalline members including the second doped semiconductor regions and transistor gates in a peripheral circuit region on the device comprise respective patterned polysilicon bodies in a single polysilicon layer.
25. The memory device of claim 14 further comprising dopant diffusion barriers between the first doped semiconductor regions and the second doped semiconductor regions.
26. The memory device of claim 25 wherein the barriers comprise SiO2.
27. The memory device of claim 25 wherein the barriers comprise SiNxOy.
28. The memory device of claim 25 wherein the barriers have thicknesses in a range about 5 to 25 Angstroms.
29. The memory device of claim 14, wherein the first doped semiconductor regions in the plurality of doped, single crystal semiconductor fins have first widths in the first direction, and the plurality of polysilicon members have second widths in the first direction, and the first widths are greater than the second widths.
30. A memory cell comprising:
a storage element, and
an access device coupled to the storage element, comprising a pn-junction between a polysilicon member of a first conductivity type, and a single crystal silicon member of a second conductivity type;
the single crystal silicon member comprising a portion of, and protruding from, a crystalline silicon body of the first conductivity type, wherein the polysilicon member and the single crystal silicon member differ in concentration of dopants and have depletion regions adjacent the interface having respective depths, and the depth of the depletion region is within the portion of the single crystal silicon member protruding from the crystalline silicon body; and
a peripheral area on a substrate including a peripheral circuit single crystal semiconductor region which is part of the crystalline silicon body that includes the single crystal silicon member, the peripheral circuit single crystal semiconductor region including a channel of an FET, a gate dielectric material on the channel and a gate, and wherein the single crystal silicon member contacts the crystalline silicon body of the first conductivity type without intervening gate dielectric material.
31. A memory cell comprising:
a storage element, and
a diode coupled as an access device to the storage element, comprising a polysilicon member of a first conductive type, a first single crystal silicon member of a second conductive type;
a dielectric layer over the polysilicon member of the diode;
an electrode extending through the dielectric layer connecting the polysilicon member of the diode to the storage element, and a metal plug through the same dielectric layer connecting the single crystal silicon member to an overlying conductor, the electrode having a top surface in contact with the storage element that is smaller than a top surface of the metal plug in contact with the overlying conductor; and
a peripheral area on a substrate including a peripheral circuit single crystal semiconductor region which is part of a crystalline silicon body that includes the first single crystal silicon member, the peripheral circuit single crystal semiconductor region including a channel of an FET, a gate dielectric material on the channel and a gate, and wherein the first single crystal silicon member contacts the crystalline silicon body of the first conductive type without intervening gate dielectric material.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. Method to generate an output audio signal y from two or more input audio signals (x1, x2, . . .) using an audio processor, this method comprising the steps of:
defining one input signal as reference signal;
for each of the other input signals, the audio processor computing gain factors related to how much of the input signal is contained in the reference signal;
the audio processor adjusting the gain factors using a limiting function; and
the audio processor computing the output signal by subtracting from the reference signal the other input signals multiplied by the corresponding adjusted gain factors.
2. Method of claim 1, wherein the output signal is scaled after it has been generated according to a scaling factor, the scaling factor being based on magnitudes of the gain factors.
3. Method of claim 1, wherein the limiting function is determined related to the desired directional response of the output signal.
4. Method of claim 1, wherein the limiting function is the minimum of the gain factor and a limit value determined related to the desired width of the response of the output signal.
5. The method of claim 1, wherein the processing is carried out in plurality of subbands as a function of time, determining gain factors in each subband.
6. The method of claim 1, wherein the processing is carried out in plurality of subbands and individual limiting functions are chosen for each subband.
7. The method of claim 1, wherein the input signals are microphone signals.
8. The method of claim 1, wherein the input signals are combinations of microphone signals.
9. The method of claim 1, wherein the input signals are combinations of B-Format signals.
10. Method of claim 1, wherein the gain factors have magnitudes which increase as an amount of the input signal that is contained in the reference signal increases.
11. Method of claim 1, wherein the gain factors are computed based on a cross-correlation between the reference signal and the input signals.
12. Device for generating an output audio signal y from two or more input audio signals (x1, x2, . . . ), this device comprising:
definition means to define one input signal as reference signal;
first calculation means to compute for each of the other input signals the gain factors related to how much of the input signal is contained in the reference signal;
adjusting means to adjust the gain factors using a limiting function; and
second calculation means to compute the output signal by subtracting from the reference signal the other input signals multiplied by the corresponding adjusted gain factors.
13. Device of claim 12, further comprising:
a scaling means to scale the output signal after it has been generated by the second calculation means according to a scaling factor, the scaling factor being based on magnitudes of the gain factors.
14. Device of claim 12, wherein the limiting function of the adjusting means is determined related to the desired directional response of the output signal.
15. Device of claim 12, further comprising:
a splitting means to convert the input signal into a plurality of subbands as a function of time, the first calculation computing the gain factors in each subband.
16. Device of claim 12, further comprising:
a splitting means to convert the input signal into a plurality of subbands as a function of time, the adjusting means using individual limiting functions for each subband.
17. Device of claim 12, wherein the gain factors have magnitudes which increase as an amount of the input signal that is contained in the reference signal increases.
18. Device of claim 12, wherein the gain factors are computed based on a cross-correlation between the reference signal and the input signals.