1. A gaming machine comprising:
a base game offering a chance of winning a payout according to a predetermined combination;
a chance game offering a chance of obtaining a chance flag which qualifies a player to join a bonus game offering a chance of winning a higher payout than the base game;
a display displaying information which is based on a timing to run the bonus game;
a storage unit storing the number of chance flags; and
a controller which is programmed to perform the steps of:
(a1) displaying on the display the information based on the timing to run the bonus game;
(a2) running the base game and the chance game at the same time;
(a3) determining and awarding a payout according to a result of the base game;
(a4) determining the number of chance flags according to a result of the chance game, and awarding a resulting number of chance flags;
(a5) accumulatively storing in the storage unit the number of chance flags awarded; and
(a6) awarding a payout determined according to a result of the bonus game which is run when the number of the chance flags stored in the storage unit equals or surpasses a predetermined number.
2. A gaming machine according to claim 1,
wherein, the controller randomly determines the timing to run the bonus game.
3. A gaming machine comprising:
a base game offering a chance of winning a payout according to a predetermined combination;
a chance game offering a chance of obtaining a chance flag which qualifies a player to join a special game offering a chance of winning a higher payout than the base game;
a display displaying information which is based on a timing to run the bonus game;
a storage unit storing the number of chance flags; and
a controller which is programmed to perform the steps of:
(b1) displaying on the display the number of the base game before the timing to run the bonus game;
(b2) running the base game and the chance game at the same time;
(b3) determining and awarding a payout according to a result of the base game;
(b4) determining the number of chance flags according to a result of the chance game, and awarding a resulting number of chance flags;
(b5) accumulatively storing in the storage unit the number of chance flags awarded; and
(b6) awarding a payout determined according to a result of the bonus game which is run when the number of the chance flags stored in the storage unit equals or surpasses a predetermined number.
4. A gaming machine comprising:
a base game offering a chance of winning a payout according to a predetermined combination;
a chance game offering a chance of obtaining a chance flag which qualifies a player to join a bonus game offering a chance of winning a higher payout than the base game;
a display displaying information which is based on a timing to run the bonus game;
a storage unit storing the number of chance flags; and
a controller which is programmed to perform the steps of:
(c1) on the display, counting down time left until the timing to run the bonus game;
(c2) running the base game and the chance game at the same time;
(c3) determining and awarding a payout according to a result of the base game;
(c4) determining the number of chance flags according to a result of the chance game, and awarding a resulting number of chance flags;
(c5) accumulatively storing in the storage unit the number of chance flags awarded; and
(c6) awarding a payout determined according to a result of the bonus game which is run when the number of the chance flags stored in the storage unit equals or surpasses a predetermined number.
5. A gaming machine, comprising:
a base game offering a chance of winning a payout according to a predetermined combination;
a chance game offering a chance of obtaining a chance flag which qualifies a player to join a bonus game offering a chance of winning a higher payout than the base game;
a display displaying information which is based on a timing to run the bonus game;
a storage unit storing the number of chance flags;
an effect producing device which produces an effect for the base game andor the chance game;
an operation device which accepts an external input operation and outputs an input signal; and
a controller which is programmed to perform the steps of:
(d1) on the display, counting down time left until the timing to run the bonus game;
(d2) running the base game and the chance game at the same time;
(d3) determining and awarding a payout according to a result of the base game;
(d4) determining the number of chance flags according to a result of the chance game, and awarding a resulting number of chance flags;
(d5) accumulatively storing in the storage unit the number of chance flags awarded;
(d6) awarding a payout determined according to a result of the bonus game which is run when the number of the chance flags stored in the storage unit equals or surpasses a predetermined number;
(d7) causing the effect producing device to produce an effect for the base game andor the chance game;
(d8) determining whether the input signal has been output from the operation device; and
(d9) if the input signal has been output, shortening the effect produced by the effect producing device.
6. A playing method of a gaming machine which includes: a base game offering a chance of winning a payout according to a predetermined combination;
a chance game offering a chance of obtaining a chance flag which qualifies a player to join a bonus game offering a chance of winning a higher payout than the base game;
a display displaying information which is based on a timing to run the bonus game; and
a storage unit storing the number of chance flags, the method comprising the steps of:
(e1) displaying on the display the number of the base game before the timing to run the bonus game;
(e2) running the base game and the chance game at the same time;
(e3) determining and awarding a payout according to a result of the base game;
(e4) determining the number of chance flags according to a result of the chance game, and awarding a resulting number of chance flags;
(e5) accumulatively storing in the storage unit the number of chance flags awarded; and
(e6) awarding a payout determined according to a result of the bonus game which is run when the number of the chance flags stored in the storage unit equals or surpasses a predetermined number.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method to configure (N) adapters interconnected to one of two or more buses disposed within a computer system, comprising the steps of:
(a) discovering each of said (N) adapters;
(b) sequentially pre-configuring each of said (N) adapters;
(c1) generating (N) configuration threads, wherein the (i)th configuration thread comprises a series of computer steps to configure the (i)th adapter disposed within a data storage and retrieval system, wherein (i) is an integer equal to or greater than 1 and equal to or less than (N);
(c2) simultaneously beginning to set device registers, load device parameters, and create interrupt vectors, for each of said (N) adapters using said (N) configuration threads; and
(d) placing said computer system in a ready state.
2. The method of claim 1, wherein each of said (N) adapters is selected from the group consisting of a host computer adapter, a data input device adapter, a data output device adapter, and a data storage device adapter.
3. The method of claim 1, wherein steps (a) and (b) further comprise the steps of:
(e) discovering the (i)th adapter;
(f) allocating system resources for the (i)th adapter; and
(g) assigning a device address for the (i)th adapter.
4. The method of claim 3, further comprising the steps of:
(h) determining if (i) equals (N); and
(j) if (i) does not equal (N), incrementing (i) and repeating steps (e), (f), (g), (h) and (j) until each of said (N) adapters has been discovered.
5. The method of claim 1, wherein steps (a) and (b) further comprise the steps of:
(k) discovering each of said (N) adapters;
(l) allocating system resources for the (i)th adapter, wherein (i) is an integer equal to or greater than 1 and equal to or less than (N); and
(m) assigning a device address for the (i)th adapter.
6. The method of claim 5, further comprising the steps of:
(n) determining if (i) equals (N); and
(o) if (i) does not equal (N), incrementing (i) and repeating steps (l), (m), (n), and (o) until system resources have been allocated for each of said (N) adapters.
7. The method of claim 6, further comprising the steps of:
(p) testing the performance of each of said (N) adapters;
(q) generating an error log; and
(r) invoking error-handling routines.
8. A method to configure (N) host computer adapters disposed within a data storage and retrieval system, wherein (N) is greater than or equal to 1, comprising the steps of:
sequentially discovering each of said (N) host computer adapters;
sequentially allocating system resources for each of said (N) host computer adapters;
sequentially assigning a device address for each of said (N) host computer adapters;
generating (N) configuration threads;
simultaneously beginning to set device registers, load device parameters, and create interrupt vectors, for each of said (N) host computer adapters using said (N) configuration threads;
terminating at different times each of said (N) configuration threads; and
placing said data storage and retrieval system in a ready state.
9. The method of claim 8, further comprising the steps of:
testing the performance of each of said (N) host computer adapters;
generating an error log; and
invoking error-handling routines.
10. A computer system comprising a computer useable medium having computer readable program code disposed therein for simultaneously configuring (N) adapters interconnected to one of two or more buses disposed within said system, the computer readable program code comprising a series of computer readable program steps to effect:
(a) discovering each of said (N) adapters;
(b) sequentially pre-configuring each of said (N) adapters;
(c1) generating (N) configuration threads, wherein the (i)th configuration thread comprises a series of computer steps to configure the (i)th adapter disposed within a data storage and retrieval system, wherein (i) is an integer equal to or greater than 1 and equal to or less than (N);
(c2) simultaneously beginning to set device registers, load device parameters, and create interrupt vectors, for each of said (N) adapters using said (N) configuration threads; and
(d) placing said computer system in a ready state.
11. The computer system of claim 10, wherein each of said a (N) adapters are selected from the group consisting of a host computer adapter, a data input device adapter, a data output device adapter, and a data storage device adapter.
12. The computer system of claim 10, wherein said computer readable program code to effect steps (a) and (b) further comprises a series of computer readable program steps to effect:
(e) discovering the (i)th adapter, wherein (i) is an integer equal to or greater than 1 and equal to or less than (N);
(f) allocating system resources for the (i)th adapter;
(g) assigning a device address for the (i)th adapter.
13. The computer system of claim 12, wherein said computer readable program code further comprises a series of computer readable program steps to effect:
(h) determining if (i) equals (N); and
(j) if (i) does not equal (N), incrementing (i) and repeating steps (e), (f), (g), (h) and (j) until each of said (N) adapters has been discovered.
14. The computer system of claim 10, wherein said computer readable program code to effect steps (a) and (b) further comprises a series of computer readable program steps to effect:
(k) discovering each of said (N) adapters;
(l) allocating system resources for the (i)th adapter, wherein (i) is an integer equal to or greater than 1 and equal to or less than (N); and
(m) assigning a device address for the (i)th adapter.
15. The computer system of claim 14, wherein said computer readable program code further comprises a series of computer readable program steps to effect:
(n) determining if (i) equals (N); and
(o) if (i) does not equal (N), incrementing (i) and repeating steps (l), (m), (n), and (o) until each of said (N) adapters has been discovered.
16. The computer system of claim 10, wherein said computer readable program code further comprises a series of computer readable program steps to effect:
(p) testing the performance of each of said (N) adapters;
(q) generating an error log; and
(r) invoking error-handling routines.
17. A data storage and retrieval system comprising a computer useable medium having computer readable program code disposed therein for simultaneously configuring (N) host computer adapters disposed within said system, the computer readable program code comprising a series of computer readable program steps to effect:
sequentially discovering each of said (N) host computer adapters;
sequentially allocating system resources for each of said (N) host computer adapters;
sequentially assigning a device address for each of said (N) host computer adapters;
generating (N) configuration threads;
simultaneously beginning to set device registers, load device parameters, and create interrupt vectors, for each of said (N) host computer adapters using said (N) configuration threads;
terminating at different times each of said (N) configuration threads; and
placing said data storage and retrieval system in a ready state.
18. The data storage and retrieval system of claim 17, wherein said computer readable program code further comprises a series of computer readable program steps to effect:
testing the performance of each of said (N) host computer adapters;
generating an error log; and
invoking error-handling routines.
19. A computer program product usable with a programmable computer processor having computer readable program code embodied therein for configuring (N) adapters interconnected to one of two or more buses disposed within a computer system, comprising:
computer readable program code which causes said programmable computer processor to discover each of said plurality of adapters;
computer readable program code which causes said programmable computer processor to sequentially pre-configure each of said plurality of adapters;
computer readable program code which causes said programmable computer processor to generate (N) configuration threads, wherein the (i)th configuration thread comprises a series of computer steps to configure the (i)th adapter disposed within a data storage and retrieval system, wherein (i) is an integer equal to or greater than 1 and equal to or less than (N);
computer readable program code which causes said programmable computer processor to simultaneously begin to set device registers, load device parameters, and create interrupt vectors, for each of said (N) adapters using said (N) configuration threads; and
computer readable program code which causes said programmable computer processor to place said computer system in a ready state.
20. The computer program product of claim 19, wherein each of said (N) adapters are selected from the group consisting of a host computer adapter, a data input device adapter, a data output device adapter, and a data storage device adapter.
21. The computer program product of claim 19, wherein computer readable program code which causes said programmable computer processor to discover each of said plurality of adapters and to sequentially pre-configure each of said plurality of adapters further comprises:
computer readable program code which causes said programmable computer processor to discover, for each value of (i), the (i)th adapter, wherein (i) is an integer equal to or greater than 1 and equal to or less than (N);
computer readable program code which causes said programmable computer processor to allocate, for each value of (i), system resources for the (i)th adapter; and
computer readable program code which causes said programmable computer processor to assign, for each value of (i), a device address for the (i)th adapter.
22. The computer program product of claim 19, wherein said computer readable program code which causes said programmable computer processor to discover each of said plurality of adapters and to sequentially pre-configure each of said plurality of adapters further comprises:
computer readable program code which causes said programmable computer processor to discover each of said (N) adapters;
computer readable program code which causes said programmable computer processor to allocate, for each value of (i), system resources for the (i)th adapter, wherein (i) is an integer equal to or greater than 1 and equal to or less than (N); and
computer readable program code which causes said programmable computer processor to assign, for each value of (i), a device address for the (i)th adapter.
23. The computer program product of claim 19, further comprising:
computer readable program code which causes said programmable computer processor to test the performance of each of said (N) adapters;
computer readable program code which causes said programmable computer processor to generate an error log; and
computer readable program code which causes said programmable computer processor to invoke error-handling routines.
24. A computer program product usable with a programmable computer processor having computer readable program code embodied therein for simultaneously configuring (N) host computer adapters disposed within a data storage and retrieval system, comprising:
computer readable program code which causes said programmable computer processor to sequentially discover each of said (N) host computer adapters;
computer readable program code which causes said programmable computer processor to sequentially allocate system resources for each of said (N) host computer adapters;
computer readable program code which causes said programmable computer processor to sequentially assign a device address for each of said (N) host computer adapters;
computer readable program code which causes said programmable computer processor to generate (N) configuration threads;
computer readable program code which causes said programmable computer processor to simultaneously begin to set device registers, load device parameters, and create interrupt vectors, for of each of said (N) host computer adapters using said (N) configuration threads;
computer readable program code which causes said programmable computer processor to terminate at different times each of said (N) configuration threads; and
computer readable program code which causes said programmable computer processor to place said data storage and retrieval system in a ready state.
25. The computer program product of claim 24, further comprising:
computer readable program code which causes said programmable computer processor to test the performance of each of said (N) host computer adapters;
computer readable program code which causes said programmable computer processor to generate an error log; and
computer readable program code which causes said programmable computer processor to invoke error-handling routines.