1. A semiconductor device having a noise-aware semiconductor cell, comprising:
a first ground network;
a second ground network that is different from the first ground network;
a first metal-oxide-semiconductor field-effect transistor (MOSFET) including:
a doped substrate,
a first source, a first gate, and a first drain forming a first source-gate-drain region in the substrate,
a first substrate tie formed in the substrate proximate the first source, and
a second substrate tie formed in the substrate proximate the first source and the first substrate tie;
a first ground rail coupled to the first source, the first substrate tie, and the first ground network; and
a second ground rail coupled to the second substrate tie and the second ground network.
2. The semiconductor device of claim 1, further comprising a second MOSFET formed adjacent the first MOSFET to form a complementary-metal-oxide-semiconductor (CMOS) semiconductor cell.
3. The semiconductor device of claim 2, further comprising a bipolar transistor formed in the substrate to form a bipolar complementary-metal-oxide-semiconductor (BiCMOS) semiconductor cell.
4. The semiconductor device of claim 2, wherein the second MOSFET comprises:
a doped well formed in the substrate;
a second source, a second gate, and a second drain forming a second source-gate-drain region in the well;
a first well tie formed in the well proximate the second source; and
a second well tie formed in the well proximate the first well tie and the second source.
5. The semiconductor device of claim 4, further comprising:
a first power rail coupled to the second source and the first well tie, and configured to be coupled to a first power network; and
a second power rail coupled to the second well tie, the second power rail configured to be coupled to a second power network.
6. The semiconductor device of claim 5, wherein the second well tie is configured within the semiconductor cell to enable a current path between the first well tie and the second well tie.
7. The semiconductor device of claim 5, wherein the second well tie is configured within the semiconductor cell to enable a current path between the second well tie and the second source-gate-drain region.
8. A noise-aware semiconductor cell, comprising:
a first metal-oxide-semiconductor field-effect transistor (MOSFET) including:
a doped substrate,
a first source, a first gate, and a first drain forming a first source-gate-drain region in the substrate,
a first substrate tie formed in the substrate proximate the first source, and
a second substrate tie formed in the substrate proximate the first source and the first substrate tie;
a first ground rail coupled to the first source and the first substrate tie, and configured to be coupled to a first ground network;
a second ground rail coupled to the second substrate tie, the second ground rail configured to be coupled to a second ground network;
a second MOSFET formed adjacent the first MOSFET;
a power rail coupled to the second MOSFET; and
a capacitive element coupled between the power rail and the first ground rail.
9. The semiconductor device of claim 1, wherein the second substrate tie is configured within the semiconductor cell to enable a current path between the second substrate tie and the first source-gate-drain region.
10. The semiconductor device of claim 1, wherein the second substrate tie is configured within the semiconductor cell to enable a first current path between the first substrate tie and the second substrate tie.
11. The semiconductor device of claim 1, further comprising a bipolar transistor formed in the substrate, the bipolar transistor including a collector proximate the second substrate tie.
12. A semiconductor device having a noise-aware semiconductor cell, comprising:
a first power network;
a second power network that is different from the first power network;
a first metal-oxide-semiconductor field-effect transistor (MOSFET) including:
a doped well,
a source, a gate, and a drain forming a source-gate-drain region in the well,
a first well tie formed in the well proximate the source, and
a second well tie formed in the well proximate the first well tie and the source;
a first power rail coupled to the source, the first well tie, and the first power network; and
a second power rail coupled to the second well tie and the second power network.
13. The semiconductor device of claim 12, wherein the second well tie is configured within the semiconductor cell to enable a current path between the second well tie and the source-gate-drain region.
14. The semiconductor device of claim 12, wherein the second well tie is configured within the semiconductor cell to enable a first current path between the first well tie and the second well tie.
15. A noise-aware semiconductor cell, comprising:
a first metal-oxide-semiconductor field-effect transistor (MOSFET) including:
a doped well,
a source, a gate, and a drain forming a source-gate-drain region in the well,
a first well tie formed in the well proximate the source, and
a second well tie formed in the well proximate the first well tie and the source;
a first power rail coupled to the source and the first well tie, and configured to be coupled to a first power network;
a second power rail coupled to the second well tie, the second power rail configured to be coupled to a second power network;
a second MOSFET including a doped substrate with the first MOSFET formed therein;
a ground rail coupled to the second MOSFET; and
a capacitive element coupled between the first power rail and the ground rail.
16. The semiconductor device of claim 15, further comprising a bipolar transistor formed adjacent the substrate.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for operating a multipoint control system, comprising:
providing the multipoint control system, wherein the multipoint control system includes a plurality of controlled units serially connected, each of the controlled units has a execution unit and an interpretive unit, each of the interpretive unit has a data processing unit and a memory unit;
transmitting an information stream by a controller, wherein the information stream includes a first start packet and a plurality of first data packets, the first start packet includes a first leading message, a first address, and a first length message;
modifying the first address by each of the data processing units of a present controlled unit included in each of the interpretive units according to the first leading message and transmitting to the next controlled unit;
retrieving the first data packet corresponding to the first address by each of the interpretive units according to the first address, the first length message; and
enabling each of the execution units included in each of the interpretive units according to content of each of the first data packets;
wherein the first data packet having long propagation delay is selectively transmitted by the controller before the first data packet having short propagation delay so as to synchronously transmit the plurality of first data packets to the controlled units.
2. The method as claimed in claim 1, wherein the controlled unit is a lighting device.
3. The method as claimed in claim 1, wherein the controlled unit comprises a LED driver and a LED.
4. The method as claimed in claim 1, wherein the information stream is composed of a clock signal and a data signal.
5. The method as claimed in claim 4, wherein the information stream is composed of signals which could be decoded to the clock signal and the data signal.
6. The method as claimed in claim 1, wherein time of arrival of the first data packet is selectively calculated by the each of the controlled unit according to the first address, the first length message and propagation delay between stages.
7. A method for operating a multipoint control system, comprising:
(1) providing the multipoint control system, wherein the multipoint control system includes a plurality of controlled units serially connected, each of the controlled units has a execution unit and an interpretive unit, each of the interpretive unit has a data processing unit and a memory unit;
(2) transmitting an information stream by a controller, wherein the information stream includes a first start packet and a plurality of first data packets, the first start packet includes a first leading message, and a first address;
(3) modifying the first address by each of the data processing units included in each of the interpretive units according to the first leading message and transmitting to the next controlled unit;
(4) retrieving the first data packet corresponding to the first address and retrieving addresses of the controlled units by each of the interpretive units according to each of the first addresses and storing address in the memory units;
(5) transmitting a second information stream to the interpretive units, the second information stream includes a second start packet and at least one second data packet, the second start packet has a second leading message and a second address; and
(6) retrieving contents of the second data packet to enable each of the execution units according to the addresses stored in the memory unit and each of the second addresses, and back to the step (5);
wherein the first data packet having long propagation delay is selectively transmitted by the controller before the first data packet having short propagation delay so as to synchronously transmit the plurality of first data packets to the controlled units.
8. The method as claimed in claim 7, wherein the controlled unit is a lighting device.
9. The method as claimed in claim 7, wherein the controlled unit comprises a LED driver and a LED.
10. The method as claimed in claim 7, the information stream is composed of a clock signal and a data signal.
11. The method as claimed in claim 10, wherein the information stream is composed of signals which could be decoded to the clock signal and the data signal.
12. The method as claimed in claim 7, wherein the second data packet having long propagation delay is selectively transmitted by the controller before the second data packet having short propagation delay so as to synchronously transmit plurality of second data packet to the controlled units.