1. A plasma display panel, comprising:
an upper substrate;
an upper dielectric layer formed on a lower surface of the upper substrate;
sustain electrodes disposed in the upper dielectric layer;
a lower substrate facing the upper substrate;
a lower dielectric layer formed on an upper surface of the lower substrate;
address electrodes formed in the lower dielectric layer so as to cross the sustain electrodes;
main barrier ribs disposed on the lower dielectric layer so as to define discharge cells corresponding to regions where the sustain electrodes and the address electrodes cross each other;
a phosphor layer formed in the discharge cells; and
dummy barrier ribs disposed at an outermost portion of the main barrier ribs, and including respective dummy units which protrude from the main barrier ribs toward an outer portion of the plasma display panel, and which are connected to each other;
wherein connection portions between the dummy units are disposed so as to overlap with at least one of terminal units of the sustain electrodes and terminal units of the address electrodes.
2. The plasma display panel of claim 1, wherein the connection portions between the dummy units are connected to the main barrier ribs.
3. The plasma display panel of claim 2, wherein the dummy barrier ribs and the main barrier ribs are formed integrally with each other.
4. The plasma display panel of claim 1, wherein the dummy barrier ribs and the main barrier ribs are formed integrally with each other.
5. The plasma display panel of claim 1, wherein the dummy units are curved and have predetermined curvatures.
6. The plasma display panel of claim 1, wherein the main barrier ribs define the discharge cells in matrix forms.
7. The plasma display panel of claim 6, wherein the discharge cells are arranged in a row at least at the outermost portion of the main barrier ribs among discharge cells corresponding to the dummy units.
8. The plasma display panel of claim 1, further comprising a sealing member for coupling the upper substrate and the lower substrate, and wherein the dummy barrier ribs are separated from the sealing member.
9. The plasma display panel of claim 1, wherein a pair of the sustain electrodes is disposed at each respective discharge cell, one of the pair of the sustain electrodes functioning as a common electrode and another of the pair of the sustain electrodes functioning as a scan electrode.
10. The plasma display panel of claim 9, wherein each of the common electrodes includes a common transparent electrode and a common bus electrode connected to the common transparent electrode, and each of the scan electrodes includes a scan transparent electrode forming a discharge gap with the common transparent electrode and a scan bus electrode connected to the scan transparent electrode.
11. The plasma display panel of claim 10, wherein terminal units of the common bus electrodes and terminal units of the scan bus electrodes are disposed so as to overlap with the connection portions between the dummy units.
12. The plasma display panel of claim 11, wherein the terminal units of the common bus electrodes and the terminal units of the scan bus electrodes extend in respective directions which are opposite to each other.
13. The plasma display panel of claim 10, wherein terminal units of the common bus electrodes and terminal units of the scan bus electrodes extend in respective directions which are opposite to each other.
14. The plasma display panel of claim 1, further comprising a protective layer formed on a lower surface of the upper dielectric layer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for determining a layout which passes testing for electrostatic discharge in a semiconductor device, comprising:
extracting an electrostatic discharge protection network comprising pads, nets and protective elements from the layout of the semiconductor device;
setting start pads and end pads from the pads in the electrostatic discharge protection network;
detecting inter-pad voltages between the start pads and the end pads and electrostatic discharge current paths along which the nets and the protective elements are arranged in a sequential order from the start pads to the end pads;
grouping, via a grouping process, the electrostatic discharge current paths along with the nets and the protective elements arranged in the sequential order of the detecting the inter-pad voltages step, wherein the grouping process includes grouping the electrostatic discharge current paths as a function of corresponding sequential order of names of elements in the one electrostatic discharge current oath including one or more of names for IO cells connected to pads, net names, protective element names, or names for IO cells to which protective elements belong;
calculating estimated values of electrostatic discharge withstand voltages between the start pads and the end pads, based on the inter-pad voltages between the start pads and the end pads and groups to which the start pads and the end pads belong, using a negative correlation between the inter-pad voltages and corresponding electrostatic withstand voltages for each group; and
providing a result indicating determination of whether the layout passes testing for electrostatic discharge, based on the estimated values.
2. The method of claim 1, wherein the grouping process groups electrostatic discharge current paths having the same names for IO cells connected to the start pads.
3. The method of claim 1, wherein the grouping process groups electrostatic discharge current paths having the same names for IO cells connected to the end pads.
4. The method of claim 1, wherein the grouping process groups electrostatic discharge current paths having the same names for IO cells to which the protective elements belong.
5. The method of claim 1,further comprising: modifying the layout when the layout fails the electrostatic discharge test.
6. The method of claim 5, further comprising: manufacturing the semiconductor device, based on the modified layout.
7. The method of claim 6, wherein the grouping process groups electrostatic discharge current paths having the same names for IO cells connected to the start pads.
8. The method of claim 5, wherein the grouping process groups electrostatic discharge current paths having the same names for IO cells connected to the start pads.
9. The method of claim 5, wherein the grouping process groups electrostatic discharge current paths having the same names for IO cells connected to the end pads.
10. The method of claim 5, wherein the grouping process groups electrostatic discharge current paths having the same names for IO cells to which the protective elements belong.
11. A method for determining a layout which passes testing for electrostatic discharge in a semiconductor device, comprising:
extracting an electrostatic discharge protection network comprising pads, nets and protective elements from the layout of the semiconductor device;
setting start pads and end pads from the pads in the electrostatic discharge protection network;
detecting inter-pad voltages between the start pads and the end pads and electrostatic discharge current paths along which the nets and the protective elements are arranged in sequential order from the start pads to the end pads;
grouping, via a grouping process, the electrostatic discharge current paths along with the nets and the protective elements arranged the sequential order of the detecting the inter-pad voltages step, wherein the grouping process includes grouping the electrostatic discharge current paths as a function of corresponding sequential order of names of elements in the one electrostatic discharge current path including one or more of names for IO cells connected to pads, net names, protective element names, or names for IO cells to which protective elements belong;
calculating estimated values of electrostatic discharge withstand voltages between the start pads and the end pads, based on the inter-pad voltages between the start pads and the end pads and groups to which the start pads and the end pads belong, via a comparison of the electrostatic discharge withstand voltages with a threshold value; and
providing a result indicating determination of whether the layout passes testing for electrostatic discharge, based on the estimated values.
12. The method of claim 11, wherein the grouping process groups electrostatic discharge current paths having the same names for IO cells connected to the start pads.
13. The method of claim 11, wherein the grouping process groups electrostatic discharge current paths having the same names for IO cells connected to the end pads.
14. The method of claim 11, wherein the grouping process groups electrostatic discharge current paths having the same names for IO cells to which the protective elements belong.
15. The method of claim 11, further comprising: modifying the layout when the layout fails the electrostatic discharge test.
16. The method of claim 15, further comprising: manufacturing the semiconductor device, based on the modified layout.
17. The method of claim 16, wherein the grouping process groups electrostatic discharge current paths having the same names for IO cells connected to the start pads.
18. The method of claim 15, wherein the grouping process groups electrostatic discharge current paths having the same names for IO cells connected to the start pads.
19. The method of claim 15, wherein the grouping process groups electrostatic discharge current paths having the same names for IO cells connected to the end pads.
20. The method of claim 15, wherein the grouping process groups electrostatic discharge current paths having the same names for IO cells to which the protective elements belong.