1. A smart storage switch multi-level-controller comprising:
a smart storage switch which comprises:
an upstream interface to a host for receiving host commands to access non-volatile memory (NVM) and for receiving host data and a host address;
a smart storage transaction manager that manages transactions from the host;
a virtual storage processor that maps the host address to an assigned NVM controller to generate a logical block address (LBA), the virtual storage processor performing a mapping for data striping;
a virtual storage bridge between the smart storage transaction manager and a LBA bus;
a volatile memory buffer for temporarily storing the host data in a volatile memory that loses data when power is disconnected;
a NVM controller, coupled to the LBA bus to receive the LBA generated by the virtual storage processor and the host data from the virtual storage bridge; and
a logical to physical address mapper, in the NVM controller, that maps the LBA to a physical block address (PBA).
2. The smart storage switch multi-level-controller of claim 1 further comprising:
a flash interface for connecting to a plurality of raw-NAND flash memory chips, the flash interface coupled to the NVM controller, for storing the host data at a block location identified by the PBA generated by the logical to physical address mapper in the NVM controller;
whereby address mapping is performed to access the raw-NAND flash memory chips.
3. The smart storage switch multi-level-controller of claim 2 further comprising:
a striping unit for distributing data segments of equal size across multiple channels of the plurality of raw-NAND flash memory chips.
4. The smart storage switch multi-level-controller of claim 3 wherein a stripe depth is equal to N times a stripe size, wherein N is a whole number of the plurality of NVM controllers, and wherein the stripe size is equal to a number of pages that are simultaneously writable into one of the plurality of NVM controllers.
5. The smart storage switch multi-level-controller of claim 2 further comprising:
a truncation process, activated on power-up, for determining a smallest size of the plurality of raw-NAND flash memory chips accessible by each NVM controller, and for setting a size of the plurality of raw-NAND flash memory chips accessible by each NVM controller to the smallest size.
6. The smart storage switch multi-level-controller of claim 3 further comprising:
means for monitoring wear-leveling by distributing data segments across multiple channels of the plurality of raw-NAND flash memory chips;
wherein the NVM controller further comprises means for wear leveling data written to the plurality of raw-NAND flash memory chips for even wear across the plurality of raw-NAND flash memory chips.
7. The smart storage switch multi-level-controller of claim 2 further comprising:
a parity unit for generating parity bits for storage with the data segments for redundant storage;
a parity and Error-Correction Code (ECC) circuit for correcting parity-bit errors occurring in data segments in a stripe read from one of the plurality of raw-NAND flash memory chips acting as a channel; and
a flash memory page ECC circuit for detecting and correcting errors occurring inside a flash memory page, wherein ECC codes are stored in a flash page spare area.
8. The smart storage switch multi-level-controller of claim 2 further comprising:
a caching circuit, implemented by the volatile memory buffer to store associated buffer data from the upstream interface, the caching circuit for transaction buffering;
wherein the NVM controller further comprises low-level means for caching data in the plurality of raw-NAND flash memory chips.
9. The smart storage switch multi-level-controller of claim 2 wherein the virtual storage processor further comprises high-level means for mapping the host data into data segments of equal size across multiple channels for storage in the plurality of raw-NAND flash memory chips;
wherein the NVM controller further comprises low-level means for mapping data written to the plurality of raw-NAND flash memory chips for distribution across the plurality of raw-NAND flash memory chips.
10. The smart storage switch multi-level-controller of claim 2 wherein the smart storage transaction manager further comprises:
an interleave unit, coupled to the virtual storage bridge, for interleaving host data to a plurality of interleaves of the plurality of NVM controllers;
a multi-channel striping unit for distributing groups of data segments of equal size across groups of multiple channels of the plurality of raw-NAND flash memory chips;
whereby the plurality of NVM controllers are accessed in interleaves.
11. The smart storage switch multi-level-controller of claim 2 wherein a non-volatile memory blocks comprise multiple flash die that are stacked together and accessible by interleaving, and wherein each of the multiple flash die comprises two planes that are accessible by interleaving;
wherein a size of the data segment is equal to multiple equal-sized pages per channel, and each channel has one of the plurality of NVM controllers, whereby the host data is striped with a depth to match the plurality of NVM controllers.
12. The smart storage switch multi-level-controller of claim 1 wherein the smart storage transaction manager further comprises:
an interleave unit, coupled to the virtual storage bridge, for interleaving host data to a plurality of interleaves of the plurality of NVM controller, whereby the plurality of NVM controllers are accessed in interleaves.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An airbag cover for a vehicle occupant restraint system comprising
an outside (12) that is visible in the installed state and an opposite inside (14),
a plastic cap (16) and
a reinforcement insert (18) that, during one of foaming and injection-molding of the plastic cap (16), is partially embedded therein and partially adjoins the plastic on an inner side and on an outer side of the reinforcement insert (18),
at least a section of the reinforcement insert (18) protruding outwards through the plastic cap (16) to the visible outside (12).
2. The airbag cover according to claim 1, wherein the section that protrudes outwards forms a decorative ring (22).
3. The airbag cover according to claim 1, wherein an emblem part (26) is provided in a center of the cap, and the emblem part (26) is positively joined to the reinforcement insert (18).
4. The airbag cover according to claim 3, wherein the emblem part (26) lies directly on the reinforcement insert (18).
5. The airbag cover according to claim 1, wherein the reinforcement insert (18) is a large-surface, prefabricated part with cutouts (19) through which the plastic cap (16) extends.
6. The airbag cover according to claim 1, wherein a material of the reinforcement insert (18) has at least one of a greater hardness and tensile strength than a material of the plastic cap (16).
7. The airbag cover according to claim 1, wherein the cover (10) has a tear line (30) and the reinforcement insert (18) extends on both sides of the tear line (30).
8. The airbag cover according to claim 7, wherein the tear line (30) extending outwards runs through the section (20) of the reinforcement insert (18) that protrudes outwards.
9. The airbag cover according to claim 1, wherein the cover (10) has a central, essentially concave area (24).
10. The airbag cover according to claim 9, wherein the concave area (24) is arranged inside the decorative ring (22).
11. The airbag cover according to claim 2, wherein a section (20) of the reinforcement insert (18) that is located inside the decorative ring (22) protrudes outwards to the outside (12).