1. A method of forming a portion of a multiplexer of a memory device, comprising:
forming a plurality of conductive plugs on a semiconductor substrate; and
forming pairs of successively adjacent first and second bit lines overlying the conductive plugs so that the first and second bit lines of a pair of successively adjacent first and second bit lines are both in contact with the same conductive plug; and
respectively coupling the first and second bit lines of each pair of successively adjacent first and second bit lines to first and second multiplexer gates.
2. The method of claim 1, wherein the first bit lines terminate within the multiplexer and the second bit lines extend exteriorly of the multiplexer.
3. The method of claim 2, wherein the conductive plugs are respectively adjacent terminal ends of the first bit lines.
4. The method of claim 2, wherein a spacer loops around an end of each of the first bit lines.
5. The method of claim 4, wherein the spacer overlies the conductive plugs.
6. The method of claim 5, wherein the spacer further overlies the first and second bit lines.
7. The method of claim 1, wherein the conductive plugs and the bit lines each contain one or more layers of conductive material.
8. The method of claim 1 further comprises forming a pair of successively adjacent third and fourth bit lines between successive pairs of successively adjacent first and second bit lines, the third and fourth bit lines overlying and in contact with an etch-stop layer that overlies the conductive plugs.
9. A method of forming a portion of a multiplexer of a memory device, comprising:
forming a plurality of conductive plugs on a semiconductor substrate; and
forming pairs of successively adjacent first and second bit lines overlying the conductive plugs so that the first and second bit lines of a pair of successively adjacent first and second bit lines are both in contact with the same conductive plug;
wherein the first bit lines terminate within the multiplexer and the second bit lines extend exteriorly of the multiplexer;
wherein a spacer loops around an end of each of the first bit lines; and
wherein the spacer overlies the conductive plugs.
10. The method of claim 9, wherein the spacer further overlies the first and second bit lines.
11. The method of claim 9, wherein the conductive plugs are respectively adjacent terminal ends of the first bit lines.
12. The method of claim 9, wherein the conductive plugs and the bit lines each contain one or more layers of conductive material.
13. A method of forming a portion of a multiplexer of a memory device, comprising:
forming a plurality of conductive plugs on a semiconductor substrate; and
forming pairs of successively adjacent first and second bit lines overlying the conductive plugs so that the first and second bit lines of a pair of successively adjacent first and second bit lines are both in contact with the same conductive plug; and
forming a pair of successively adjacent third and fourth bit lines between successive pairs of successively adjacent first and second bit lines, the third and fourth bit lines overlying and in contact with an etch-stop layer that overlies the conductive plugs.
14. The method of claim 13, wherein the first bit lines terminate within the multiplexer and the second bit lines extend exteriorly of the multiplexer.
15. The method of claim 13, wherein the conductive plugs are respectively adjacent terminal ends of the first bit lines.
16. The method of claim 13, wherein a spacer loops around an end of each of the first bit lines.
17. The method of claim 16, wherein the spacer overlies the conductive plugs.
18. The method of claim 17, wherein the spacer further overlies the first and second bit lines.
19. The method of claim 13, wherein the conductive plugs and the bit lines each contain one or more layers of conductive material.
20. A method of forming a portion of a multiplexer of a memory device, comprising:
forming a plurality of first conductive plugs on a semiconductor substrate;
forming a first insulation layer overlying the plurality of first conductive plugs;
forming an etch-stop layer overlying the first insulation layer;
removing portions of the etch-stop layer to expose portions of the first insulation layer;
forming a second insulation layer overlying the etch-stop layer and the exposed portions of the first insulation layer;
forming first and second bit lines through the first and second insulation layers so that a pair of successively adjacent first and second bit lines are both in contact with a first conductive plug; and
forming pairs of successively adjacent third and fourth bit lines through the second insulation material so that the pairs of successively adjacent third and fourth bit lines are in contact with the etch stop layer at locations adjacent the first conductive plugs;
wherein a pair of successively adjacent third and fourth bit lines are located between successive pairs of successively adjacent first and second bit lines.
21. The method of claim 20 further comprises forming a plurality of second conductive plugs on the semiconductor substrate for respectively coupling the pairs of successively adjacent third and fourth bit lines.
22. The method of claim 20, wherein the first and third bit lines terminate within the multiplexer and the second and fourth bit lines extend exteriorly of the multiplexer.
23. The method of claim 22, wherein the first bit lines terminate within the multiplexer at first distance from an end of the multiplexer and the third bit lines terminate within the multiplexer at second distance from the end of the multiplexer, the second distance being different from the first distance.
24. The method of claim 22, wherein a dielectric spacer loops around an end of each of the first and third bit lines.
25. The method of claim 24, wherein the dielectric spacer overlies the first conductive plugs.
26. The method of claim 25, wherein the dielectric spacer further overlies the first, second, third, and fourth bit lines.
27. The method of claim 20 further comprises respectively coupling the first and second bit lines of each pair of successively adjacent first and second bit lines to first and second multiplexer gates and respectively coupling the third and fourth bit lines of each pair of successively adjacent third and fourth bit lines to third and fourth multiplexer gates.
28. The method of claim 20, wherein forming the plurality of first conductive plugs on the semiconductor substrate comprises forming the conductive plugs through a third insulation layer interposed between the semiconductor substrate and the first insulation layer.
29. A method of forming a portion of a multiplexer of a memory device, comprising:
forming a first insulation layer on a semiconductor substrate;
forming a plurality of holes through the first insulation layer that expose the semiconductor substrate;
forming a conductive plug in each of the holes in contact with the semiconductor substrate;
forming a second insulation layer overlying the conductive plugs;
forming an etch-stop layer on the second insulation layer;
removing portions of the etch-stop layer to expose portions of the second insulation layer;
forming a third insulation layer overlying the etch-stop layer and the exposed portions of the second insulation layer;
forming pairs of successively adjacent first and second trenches through the second and third insulation layers so that a pair of successively adjacent first and trenches exposes portions of each conductive plug;
forming a pair of successively adjacent third and fourth trenches through the third insulation layer between successive pairs of successively adjacent pairs first and second trenches to expose portions of the etch stop layer;
respectively forming first and second bit lines in the first and second trenches so that a pair of successively adjacent first and second bit lines is contact with each of the conductive plugs; and
respectively forming third and fourth bit lines in the third and fourth trenches so that the third and fourth bit lines are in contact with the etch stop layer and so that a pair of successively adjacent third and fourth bit lines is formed between successive pairs of successively adjacent first and second bit lines.
30. The method of claim 29 further comprises patterning the third insulation layer with a plurality of spacers, before forming the first, second, third, and fourth trenches, for exposing portions of the third insulation layer corresponding to the first, second, third, and fourth trenches for removal.
31. The method of claim 30, wherein patterning the third insulation layer with a plurality of spacers, comprises:
forming a plurality of mask segments on the third insulation layer;
forming the spacers on sidewalls and a end wall of each of the mask segments; and
removing the mask segments so as to leave the spacers on the third insulation layer.
32. The method of claim 29, wherein the first, second, and third insulation layers are of the same material.
33. The method of claim 29, wherein:
the first and second bit lines of each pair of successively adjacent first and second bit lines each comprise a first conductive layer formed on a respective one of the conductive plugs and a second conductive layer formed on the first conductive layer; and
the third and fourth bit lines each comprise the first conductive layer formed on the etch-stop layer and the second conductive layer formed on the first conductive layer.
34. The method of claim 29, wherein the first and third bit lines terminate within the multiplexer and the second and fourth bit lines extend exteriorly of the multiplexer.
35. The method of claim 34, wherein a dielectric spacer loops around an end of each of the first and third bit lines.
36. The method of claim 29, wherein a dielectric spacer overlies the conductive plugs.
37. The method of claim 36, wherein the dielectric spacer further overlies the first, second, third, and fourth bit lines.
38. The method of claim 29 further comprises respectively coupling the first and second bit lines of each pair of successively adjacent first and second bit lines to first and second multiplexer gates and respectively coupling the third and fourth bit lines of each pair of successively adjacent third and fourth bit lines to third and fourth multiplexer gates.
39. A method of forming a portion of a multiplexer of a memory device, comprising:
forming a first insulation layer on a semiconductor substrate;
patterning the first insulation layer for exposing portions of the first insulation layer for removal;
removing the exposed portions of the first insulation layer to form a plurality of holes through the first insulation layer that expose the semiconductor substrate;
forming a conductive plug in each of the holes in contact with the semiconductor substrate;
forming a second insulation layer overlying the conductive plugs;
forming an etch-stop layer on the second insulation layer;
patterning the etch-stop layer for exposing portions of the etch-stop layer for removal;
removing the exposed portions of the etch-stop layer to expose portions of the second insulation layer;
forming a third insulation layer overlying the etch-stop layer and the exposed portions of the second insulation layer;
forming a plurality of mask segments on the third insulation layer;
forming a dielectric layer overlying the mask segments and the third insulation layer;
anisotropically removing portions of the dielectric layer such that remaining portions of the dielectric layer self align with and are disposed on sidewalls and an end wall of each the mask segments;
removing the mask segments, leaving the spacers, wherein the spacers form a pattern for respectively exposing portions of the third insulation layer for removal;
removing the exposed portions of the third insulation layer to form pairs of successively adjacent first and second trenches through the third insulation layer to expose portions of the second insulation layer, and forming a pair of successively adjacent third and fourth trenches through the third insulation layer between successive pairs of successively adjacent pairs first and second trenches to expose portions of the etch stop layer;
removing the exposed portions of the second insulation layer, thereby extending the pairs of successively adjacent first and second trenches so that a pair of successively adjacent first and trenches exposes portions of each conductive plug;
respectively forming first and second bit lines in the first and second trenches so that a pair of successively adjacent first and second bit lines is contact with each of the conductive plugs; and
respectively forming third and fourth bit lines in the third and fourth trenches so that the third and fourth bit lines are in contact with the etch stop layer and so that a pair of successively adjacent third and fourth bit lines is formed between successive pairs of successively adjacent first and second bit lines.
40. The method of claim 39, wherein removing the exposed portions of the first insulation layer comprises an anisotropic dry etch.
41. The method of claim 39, wherein removing the exposed portions of the etch-stop layer comprises an etch selective to the etch-stop layer.
42. The method of claim 41, wherein removing the exposed portions of the etch-stop layer comprises an anisotropic dry etch.
43. The method of claim 39, wherein removing the exposed portions of the second and third insulation layers comprises an anisotropic dry etch.
44. The method of claim 39, wherein removing the mask segments comprises an etch selective to the mask segments.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A jewel comprising a volume of transparent amorphous vitreous material of the crystal type, whereof a portion of the external surface is coated with successive layers of metal or ceramic particles designed to provide it with a decorative dichroic visual effect when said portion is observed through the volume of the transparent material,
wherein the succession of the layers observes the following scheme:
at least one alternation of two transparent layers of metal andor ceramic particles in contact with the crystal; then
a final reflecting opaque layer consisting of metal;
said final reflecting opaque layer allowing reflectance and preventing transmittance of light.
2. The jewel according to claim 1, wherein the metal forming the final opaque layer is titanium (Ti).
3. The jewel according to claim 1, wherein the metal forming the final opaque layer is chromium (Cr).
4. The jewel according to claim 1, wherein the succession of layers includes one or two alternations of two layers of metal or ceramic particles.
5. The jewel according to claim 1, wherein the alternation(s) of layers each consist(s) of a pair formed with a SiO2 layer and a TiO2 layer.
6. The jewel according to claim 1, wherein the alternation(s) of layers each consist(s) of a pair formed with an MgF2 layer and Cr layer.
7. The jewel according to claim 1, wherein the final opaque layer has a thickness larger than or equal to 50 nm.
8. The jewel according to claim 1, wherein the thickness of the first layer of each alternation is between 50 and 500 nm.
9. The jewel according to claim 1, wherein the thickness of the second layer of each alternation is between 90 and 400 nm.
10. The jewel according to claim 1, wherein the crystal volume is a cabochon on a surface of which the succession of layers is applied.
11. The jewel according to claim 1, wherein at least one layer of the two transparent layers is of ceramic particles.
12. The jewel according to claim 1, wherein the two transparent layers are of ceramic particles.