1. A sense amplifier comprising:
a comparator including a first input coupled to a reference voltage node, including a second input coupled to a data voltage node, and including an output providing a signal indicative of a difference in voltages on the reference and data voltage nodes;
a first load circuit coupled to the reference voltage node to load a reference cell;
a second load circuit coupled to the data voltage node to load a data cell;
a low impedance circuit coupled to the first input.
2. The sense amplifier of claim 1 wherein the first load circuit is a PMOS transistor including a source terminal coupled to a supply voltage terminal, including a drain coupled to the reference voltage node, and including a gate coupled to a control signal node,
wherein the second load circuit comprises a reference current source,
wherein the low impedance circuit comprises a first resistor including a first terminal coupled to the supply voltage node and including a second terminal coupled to the first input of the comparator, and comprises a second resistor including a first terminal coupled to the second terminal of the first resistor and including a second terminal coupled to a ground node.
3. The sense amplifier of claim 2 further comprising a first switch coupled between the first and second inputs of the comparator to selectively couple said first and second inputs.
4. The sense amplifier of claim 3 further comprising a second switch coupled between the reference voltage node and the first input of the comparator to selectively couple the reference voltage node to the first input.
5. The sense amplifier of claim 4 wherein the low impedance circuit further comprises a third resistor including a first terminal coupled to the first terminal of the second resistor and including a second terminal coupled to the ground node, comprises a fourth resistor including a first terminal and including a second terminal coupled to the first terminal of the third resistor, and further comprises a second PMOS transistor including a source terminal coupled to the supply voltage node, including drain terminal coupled to the first terminal of the fourth resistor, and including a gate coupled to an enable signal.
6. The sense amplifier of claim 1 wherein the first load circuit is disposed adjacent said reference cell, the second load circuit is disposed adjacent said data cell.
7. The sense amplifier of claim 6 wherein the reference cell is disposed outside of an array that includes the data cell.
8. The sense amplifier of claim 1 further comprising a holding circuit for maintaining the voltage on the first input of the comparator.
9. The sense amplifier of claim 8 wherein the holding circuit comprises a capacitor coupled between the first input of the comparator and a ground node.
10. The sense amplifier of claim 1 wherein the low impedance circuit comprises:
a first resistor including first and second terminals coupled to the first input of the comparator and a ground node, respectively;
a second resistor including a first terminal and including a second terminal coupled to the first input of the comparator;
a MOS transistor including first and second terminals spaced apart with a channel therebetween and including a gate for controlling current in said channel, said first terminal being coupled to a supply voltage node, said second terminal being coupled to the first terminal of the second resistor, said gate being coupled to a reference supply voltage node.
11. The sense amplifier of claim 10 wherein the low impedance circuit further comprises a filter coupled between the reference supply voltage node and the gate of the MOS transistor.
12. The sense amplifier of claim 1 further comprising a control circuit coupled to the first and second load circuits to control the loading on the reference voltage node and the data reference nodes, respectively, in response to voltages on the reference and data voltage nodes.
13. The sense amplifier of claim 12 wherein the control circuit includes an operational amplifier.
14-16. (canceled)
17. A sense amplifier comprising:
a first load circuit coupled to a reference voltage node to load a reference cell;
a second load circuit coupled to the first load circuit and coupled to the data voltage node to load a data cell in response to the first load circuit;
a low impedance circuit; and
a comparator including a first input coupled to the low impedance circuit, including a second input coupled to the data voltage node, and including an output providing a signal indicative of the difference in voltages on the first and second inputs.
18. The sense amplifier of claim 17 wherein the low impedance circuit comprises
a first resistor including a first terminal coupled to a supply voltage node and including a second terminal coupled to the first input of the comparator; and
a second resistor including a first terminal coupled to the second terminal of the first resistor and including a second terminal coupled to a ground node.
19. The sense amplifier of claim 17 wherein the first load circuit comprises a first PMOS transistor including first and second terminals spaced apart with a channel there between and including a gate for controlling current in said channel, said first terminal being coupled to the voltage supply node, said second terminal being coupled to said gate and to the reference voltage node,
wherein the second load circuit comprises a second PMOS transistor including first and second terminals spaced apart with a channel therebetween and including a gate for controlling current in said channel, said first terminal being coupled to the supply voltage node, said second terminal being coupled to the second input of the comparator and to the data voltage node, said gate being coupled to the second terminal of the first PMOS transistor.
20. The sense amplifier of claim 18 wherein the second load circuit further comprises a third PMOS transistor including first and second terminals spaced apart with a channel therebetween and including a gate for controlling current in said channel, said first terminal being coupled to the supply voltage node, said second terminal being coupled to said gate and to said second terminal of the second PMOS transistor.
21. The sense amplifier of claim 17 wherein the low impedance circuit comprises a NMOS transistor including first and second terminals spaced apart with a channel therebetween and including a gate for controlling current in said channel, said first terminal being coupled to the supply voltage node, said second terminal being coupled to the first input of the comparator, said gate being coupled to the second terminal of the first PMOS transistor; and
a first resistor including a first terminal coupled to the second terminal of the NMOS transistor and to the first input of the comparator and including a second terminal coupled to the ground node.
22-73. (canceled)
74. The sense amplifier of claim 1, further comprising a capacitor coupled to the comparator to hold a reference voltage level of the comparator during sensing.
75. The sense amplifier of claim 74, wherein the capacitor is a floating capacitor coupled to an input of the comparator.
76. The sense amplifier of claim 1, further comprising one or more filter components configured to generate a filtered bias voltage for use by the sense amplifier.
77. The sense amplifier of claim 1, wherein the low impedance circuit is configured to selectively apply a voltage to an input of the comparator.
78. The sense amplifier of claim 17, further comprising a capacitor coupled to the comparator to hold a reference voltage level of the comparator during sensing.
79. The sense amplifier of claim 78, wherein the capacitor is a floating capacitor coupled to an input of the comparator.
80. The sense amplifier of claim 17, further comprising one or more filter components configured to generate a filtered bias voltage for use by the sense amplifier.
81. The sense amplifier of claim 17, wherein the low impedance circuit is configured to selectively apply a voltage to an input of the comparator.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A process for producing a partially low-fat flour having a high content of stabilized polyunsaturated fatty acid, comprising the steps of:
selecting a plurality of Salvia Hispanica L. seeds;
incorporating the plurality of Salvia Hispanica L. seeds into pressing equipment;
pressing under temperature control the plurality of Salvia Hispanica L. seeds with the pressing equipment where i) a ratio between polyunsaturated fatty acids and antioxidants of the Salvia Hispanica L. seeds is changed, and ii) an oil and an expeller sub-product is formed therefrom;
cooling the expeller sub-product to room temperature; and
grinding the expeller sub-product, already at room temperature, to obtain a different particle size to form a partially low-fat flour with a high content of polyunsaturated fatty acids.
2. The process of claim 1, wherein the stabilized polyunsaturated fatty acid is an \u03a93 polyunsaturated fatty acid.
3. The process of claim 1, wherein the oil is a mixture of oils selected from a group consisting of i-caryophyllene, i-bourbonene, i-pinene, widdrol, germacrene, linalool, valencene, muurolene, globulol, a-humulene, t-cadinol and mixtures thereof.
4. The process of claim 1, wherein the polyunsaturated fatty acids further comprises multiple vitamins and macro-elements.
5. The process of claim 4, wherein at least one of the multiple vitamins is selected from a group consisting of vitamin A, niacin, riboflavin and thiamin.
6. The process of claim 4, wherein the macro-elements are selected from a group consisting of calcium, potassium, magnesium, phosphorus, aluminum, boron, copper manganese, molybdenum and zinc.
7. The process of claim 1, wherein the polyunsaturated fatty acids comprise up to 7 wt % of oleic acid, up to 23 wt % of linoleic acid, up to 63 wt % of alpha-linolenic acid, up to 7 wt % of palmitic acid, up to 3 wt % of stearic acid, and less than a tenth part percent of myristic acid.
8. The process of claim 1, wherein the pressing equipment is a screw extruder which gradually presses the seeds such that the molecular cis-cis structure of the polyunsaturated fatty acids are preserved.
9. The process of claim 1, wherein the step of pressing step concentrates and preserves the antioxidants.
10. The process of claim 1, wherein the step of grinding is accomplished by a disc-driven mill.
11. The process of claim 1, wherein the step of pressing includes a working temperature that is maintained below \u221245\xb0 C.
12. The process of claim 1, wherein the changed ratio between polyunsaturated fatty acids and antioxidants is modified by reducing the weight percentage of polyunsaturated fatty acids.
13. A expeller sub-product made from pressed Salvia Hispanica L. seeds, obtained from the process of claim 1, comprising polyunsaturated fatty acids and antioxidants.
14. The expeller sub-product of claim 13, wherein the expeller sub-product further comprises up to 29 wt % of fatty matter, up to 27 wt % of protein, and up to 34 wt % of dietary fiber, of which at least 40 wt % is insoluble dietary fiber.
15. The expeller sub-product of claim 13, wherein the polyunsaturated fatty acids include up to 7 wt % of oleic acid, up to 23 wt % of linoleic acid, up to 63 wt % of alpha-linolenic acid, up to 7 wt % of palmitic acid, up to 3 wt % of stearic acid, and less than a thenth of a part of myristic acid.
16. The expeller sub-product of claim 13, wherein the polyunsaturated fatty acids further comprises multiple vitamins and macro-elements.
17. The process of claim 16, wherein at least one of the multiple vitamins is selected from a group consisting of vitamin A, niacin, riboflavin and thiamin.
18. The process of claim 16, wherein the macro-elements are selected from a group consisting of calcium, potassium, magnesium, phosphorus, aluminum, boron, copper manganese, molybdenum and zinc.
19. A method for incorporating the expeller sub-product of claim 13, comprising:
mixing in a mixer until homogenized the expeller sub-product with at least one product select from a group consisting of wheat flour, corn flour, soy flour, cereal flour, legume flour, meat based paste, vegetable based paste, dairy products and mixtures thereof; and
cooking the homogenized mixture.
20. The method of claim 19, wherein the expeller sub-product represents up to at least 90 wt % of the homogenized mixture.
21. A partially low-fat flour having a high content of stabilized polyunsaturated fatty acid produced by the process of claim 1, wherein the partially low-fat flour comprises 3\u201329 wt % fats, 16\u201327 wt % protein, and 20\u201334 wt % dietary fiber, of which at least 40 wt % is insoluble dietary fiber.
22. The partially low-fat flour of claim 21, wherein the protein includes at least one amino acid selected from the group consisting of threonine, lysine and leucine.
23. A partially low-fat flour of claim 21, wherein the low-fat flour provides 19\u201321 wt % of fat, 21\u201323 wt % of protein and 25\u201327 wt % of dietary fiber, of which at least 40 wt % is insoluble dietary fiber.
24. A method for incorporating the partially low-fat flour product of claim 21 into various food products, comprising:
mixing in a mixer until homogenized the partially low-fat flour with at least one food product selected from a group consisting of wheat flour, corn flour, soy flour, cereal flour, legume flour, meat based paste, vegetable based paste, dairy products and mixtures thereof; and
cooking the homogenized mixture.
25. The method of claim 24 wherein the partially low-fat flour having a high content of stabilized polyunsaturated fatty acids represents 1\u20134 wt % of the homogenized mixture.