1. A semiconductor memory device comprising:
at least one dummy cell block including dummy cells and memory cells;
normal bit lines to connect the memory cells in the dummy cell block in a first direction;
dummy bit lines to connect the dummy cells in the first direction; and
a dummy sense amplifier connecting any two of the normal bit lines and the dummy bit lines.
2. The device according to claim 1, where the dummy sense amplifier is connected between one of the normal bit lines and one of the dummy bit lines.
3. The device according to claim 2, where the dummy sense amplifier is structured to store data in at least one of the dummy cells in the dummy cell block that is complementary to data stored in at least one of the memory cells in the dummy cell block.
4. The device according to claim 3, where the dummy sense amplifier senses and amplifies data developed in the normal bit line using a voltage corresponding to data developed in the dummy bit line as a reference voltage.
5. The device according to claim 1, where the dummy bit lines and the normal bit lines are alternately laid out in a second direction of the cell block.
6. The device according to claim 5, comprising:
at least one normal sense amplifier; and
a normal cell block adjacent to the dummy cell block, the normal memory cell block including a plurality of normal memory cells, where the normal bit lines are connected to second normal bit lines in the normal memory cell block via the normal sense amplifier.
7. The device according to claim 6, where the normal sense amplifier and the dummy sense amplifier have the same structure.
8. The device according to claim 1, where the dummy sense amplifier is connected between any two of the dummy bit lines.
9. The device according to claim 8, where the dummy sense amplifier is structured to operate when one of the memory cells connected to the normal bit lines fails.
10. The device according to claim 9, where adjacent cells in a second direction among the dummy cells and the memory cells are connected to one another by a plurality of word lines.
11. The device according to claim 10, where dummy cells sharing one dummy sense amplifier and one word line among the dummy cells operate to store complementary data.
12. The device according to claim 8, where the dummy sense amplifier senses and amplifies data developed in one of the two dummy bit lines connected to the dummy sense amplifier using a voltage corresponding to data developed in the other dummy bit line as a reference voltage.
13. The device according to claim 8, where the dummy bit lines and the normal bit lines are alternately laid out in a second direction of the dummy cell block.
14. The device according to claim 8, comprising:
at least one normal sense amplifier; and
a normal cell block adjacent to the dummy cell block, the normal memory cell block including a plurality of normal memory cells, where the normal bit lines are connected to second normal bit lines in the normal memory cell block via the normal sense amplifier.
15. A semiconductor memory device comprising:
dummy cell blocks each including a plurality of memory cells and a plurality of dummy cells;
a plurality of normal memory cell blocks laid out between the dummy cell blocks, each of the normal memory cell blocks including a plurality of memory cells;
normal sense amplifier blocks laid out between each of the normal memory cell blocks and between each of the dummy cell blocks and the plurality of normal memory cell blocks; and
dummy sense amplifier blocks laid out to respectively connect the memory cells and the dummy cells in the dummy cell blocks.
16. The device according to claim 15, where each normal memory cell block comprises a plurality of normal bit lines laid out in a second direction, the normal bit lines respectively connecting between portions of the plurality of memory cells in a first direction.
17. The device according to claim 16, where the dummy cell block comprises normal bit lines for connecting between a plurality of memory cells in the first direction, and dummy bit lines for connecting between a plurality of dummy cells in the first direction, the normal bit lines and the dummy bit lines being alternately laid out in the second direction.
18. The device according to claim 17, where each of the dummy sense amplifier blocks comprise a plurality of dummy sense amplifiers laid out to respectively connect the normal bit lines with the dummy bit lines from the adjacent dummy cell block.
19. The device according to claim 18, where each of the dummy sense amplifiers is structured to store data in at least one of the dummy cells in the dummy cell block that is complementary to data stored in at least one of the memory cells in the dummy cell block, and where the dummy cells respectively have the same address as the memory cells.
20. The device according to claim 19, where the dummy sense amplifier senses and amplifies data developed in the normal bit line using a voltage corresponding to data developed in the dummy bit line as a reference voltage.
21. The device according to claim 17, where the normal sense amplifier block comprises a plurality of normal sense amplifiers each connected between a normal bit line of a first normal memory cell block and a normal bit line of a second normal memory cell block when the first and second normal memory cell blocks are adjacent to each other, and between a normal bit line in a normal memory cell block and a normal bit line in a dummy cell block when the normal memory cell block and the dummy cell block are adjacent to each other.
22. A semiconductor memory device comprising:
dummy cell blocks each including a plurality of memory cells and a plurality of dummy cells;
a plurality of normal memory cell blocks laid out between the dummy cell blocks, each of the normal memory cell blocks including a plurality of memory cells;
normal sense amplifier blocks laid out between each of the normal memory cell blocks and between each of the dummy cell blocks and the plurality of normal memory cell blocks; and
dummy sense amplifier blocks each including dummy sense amplifiers laid out to each connect dummy cells spaced apart by at least one memory cell in each dummy cell block.
23. The device according to claim 22, where each normal memory cell block comprises a plurality of normal bit lines laid out in a second direction, the normal bit lines respectively connecting between portions of the plurality of memory cells in a first direction.
24. The device according to claim 23, where the dummy cell block comprises normal bit lines for connecting between a plurality of memory cells in the first direction, and dummy bit lines for connecting between a plurality of dummy cells in the first direction, the normal bit lines and the dummy bit lines being alternately laid out in the second direction.
25. The device according to claim 24, where each of the dummy sense amplifiers in the dummy sense amplifier blocks are laid out for connecting between at least two of the dummy bit lines.
26. The device according to claim 25, where the dummy sense amplifier block is structured to operate when one of the memory cells connected to the normal bit lines in the dummy cell block fails.
27. The device according to claim 26, where two dummy cells having the same address among the dummy cells connected to any dummy sense amplifiers in the dummy sense amplifier block store complementary data.
28. The device according to claim 27, where the dummy sense amplifiers in the dummy sense amplifier blocks sense and amplify data developed in one of two dummy bit lines connected to the dummy sense amplifier using a voltage corresponding to data developed in the other dummy bit line as a reference voltage.
29. The device according to claim 22, where each normal sense amplifier block comprises a plurality of normal sense amplifiers each connected between a normal bit line of a first normal memory cell block and a normal bit line of a second normal memory block when the first and second normal memory cell blocks are adjacent to each other, and between a normal bit line in a normal memory cell block and a normal bit line in a dummy cell block when the normal memory cell block and the dummy cell block are adjacent to each other.
30. The device according to claim 24, comprising a plurality of switching devices each respectively connected to the dummy bit lines between each of the dummy cell blocks and each of the dummy sense amplifier blocks, where the plurality of switching devices are further connected to a repair signal line.
31. A method of storing data in a memory cell in a dummy cell block including a dummy cell and the memory cell, the method comprising:
applying a voltage corresponding to the data to be stored to the memory cell in the dummy cell block via a normal sense amplifier; and
substantially simultaneously applying a voltage complementary to the voltage corresponding to the data to be stored in the memory cell to the dummy cell in the dummy cell block via a dummy sense amplifier.
32. The method of claim 31 where applying the voltage corresponding to the data to be stored comprises:
enabling a word line connected to the memory cell; and
applying the voltage corresponding to the data to be stored to a bit line connected between the normal sense amplifier and the memory cell.
33. The method of claim 32, where substantially simultaneously applying a voltage complementary to the voltage corresponding to the data to be stored comprises:
applying the voltage corresponding to the data to be stored to the dummy sense amplifier;
inverting the voltage corresponding to the data to be stored in the dummy sense amplifier; and
applying the complementary voltage to the dummy cell from the dummy sense amplifier.
34. The method of claim 32, where the dummy cell block includes a second dummy cell and where applying a voltage complementary to the voltage corresponding to the data to be stored comprises:
inverting the voltage corresponding to the data to be stored in the dummy sense amplifier;
applying the voltage corresponding to the data to be stored to the dummy cell from the dummy sense amplifier; and
applying the complementary voltage to the second dummy cell from the dummy sense amplifier.
35. A method for sensing data in a memory cell in a dummy cell block including a dummy cell and the memory cell, where data stored in the dummy cell is complementary to data stored in the memory cell, the method comprising:
sensing and amplifying the data in the memory cell through a dummy sense amplifier using a voltage corresponding to the data in the dummy cell as a reference voltage; and
outputting the sensed and amplified data through a normal sense amplifier connected to the memory cell.
36. The method according to claim 34, where the dummy cell block comprises a second dummy cell that stores data similar to the data stored in the memory cell and where the dummy sense amplifier senses and amplifies the data in the second dummy cell using a voltage corresponding to the data in the dummy cell as a reference voltage.
37. A method of repairing a memory cell in a dummy cell block including a first dummy cell, a second dummy cell, and the memory cell, where data stored in the first dummy cell is complementary to the data stored in the second dummy cell, the method comprising:
blocking a connection on a normal bit line connected between the memory cell and a normal sense amplifier;
connecting the first and second dummy cells to a dummy sense amplifier in a first dummy sense amplifier block in response to a repair signal; and
operating the dummy sense amplifier to substitute the dummy cell for the memory cell.
38. The method of claim 37, where blocking the connection on the normal bit line includes activating a switching device responsive to a signal notifying a fail occurrence.
39. The method of claim 37, further comprising connecting the first and second dummy cells to a dummy sense amplifier in a second dummy sense amplifier block in response to the repair signal.
40. The method of claim 39, where the first and second dummy sense amplifier blocks each include a plurality of dummy amplifiers that are all enabled in response to the repair signal.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An organizer for holding various wait staff tools comprising:
a first planar section, said first planer section having a first exterior section, a first interior section, a first side edge and a second side edge;
a second planar section, said second planar section having a second exterior section, a second interior section, a third side edge, and a fourth side edge;
said first planar section and said second planar section being attachable along the first side edge and the third side edge, wherein said attachment provides for the first planar section to fold respectively toward the second planar section forming a receptacle therebetween;
the receptacle comprising said first interior section and said second interior section; and
a plurality of pockets of varying dimensions formed on or in said first interior section andor said second interior section.
2. The organizer of claim 1, wherein the plurality of pockets comprise members secured to the first interior section andor said second interior section.
3. The plurality of pockets of claim 2, wherein members are secured to the first interior section andor said second interior section by one or more sides of the pockets.
4. The organizer of claim 1, wherein said first planar section and said second planar section are integrally attached.
5. The organizer of claim 1, wherein said first planar section and said second planar section are detachably attached.
6. The organizer of claim 1, wherein said first planar section and said second planar section are fixedly attached.
7. The organizer of claim 1, further comprising a plurality of pockets of varying dimensions formed on or in said first exterior section andor said second exterior section.
8. The organizer of claim 1, wherein the plurality of pockets comprise substantially transparent andor translucent members.
9. The organizer of claim 1, wherein the plurality of pockets comprise substantially opaque members.
10. The organizer of claim 1, wherein tools are selected from the group consisting of writing instruments, writing utensils, paper currency, coins, paper, order slips, lighters, bottle openers, writing tablets, PDA’s, wine keys, and combinations thereof.
11. The organizer of claim 1, further comprising a third planar section.
12. The third planar section of claim 11, wherein said third planar section is attached to the first exterior section.
13. The third planar section of claim 11, wherein said third planar section is attached to the second exterior section.
14. The third planar section of claim 11, wherein said third planar section comprises letters andor designs printed or otherwise affixed thereto.
15. The organizer of claim 11, further comprising a fourth planar section, wherein said third planar section is attached to either said first exterior section or said second exterior section and said and fourth planar section is attached to the other said first or second exterior section.
16. An organizer for holding various tools comprising:
a cover having a first side and a second side; each of said first side and said second side having an exterior surface and an interior surface, wherein the exterior surfaces folds over the interior surfaces to secure the interior surface; and
a plurality of pockets of varying dimensions residing throughout the interior surface of the cover for holding various tools.
17. The organizer of claim 16, further comprising a plurality of pockets of varying dimensions formed on or in said exterior surface of said first side andor second side.
18. The organizer of claim 16, further comprising said first side having at least one edge and said second side having at least one edge, wherein said first side and said second side are integrally attached adjacent to said respective edges.
19. The organizer of claim 16, further comprising said first side having at least one edge and said second side having at least one edge, wherein said first side and said second side are detachably attached adjacent to said respective edges.
20. A method of utilizing an organizer for holding various wait staff tools to provide wait staff service comprising the steps of:
providing a first planar section, said first planer section having a first exterior section, a first interior section, a first side edge and a second side edge;
providing a second planar section, said second planar section having a second exterior section, a second interior section, a third side edge, and a fourth side edge;
attaching said first planar section and said second planar section along the first side edge and the third side edge
folding the first planar section toward the second planar section, wherein said folding forms a receptacle therebetween, and where said receptacle comprises said first interior section and said second interior section;
providing a plurality of pockets of varying dimensions formed on or in said first interior section andor said second interior section;
placing wait staff tools in said plurality of pockets;
retaining said plurality of tools within said pockets andor within said organizer; and
storing said organizer on said wait staffs person while serving patrons.