1. A flash memory comprising:
a local row decoder circuit configured to drive word lines coupled to a bank of a flash memory responsive to separate read and write control signals provided thereto from outside the local row decoder circuit; and
a global row decoder circuit, coupled to the local row decoder circuit via the separate read and write control signals, and configured to activate the separate read and write control signals based on an address provided to the global row decoder circuit that indicates memory cells associated with the address are accessed using the word lines.
2. A flash memory according to claim 1 wherein the local row decoder circuit comprises a first local row decoder circuit, the bank comprises a first bank, and the word lines comprise first word lines, the flash memory further comprising:
a second local row decoder circuit configured drive to a second bank of the flash memory, separate from the first bank, via second word lines that are separate from the first word lines, wherein the second local row decoder circuit is coupled to the global decoder circuit by the separate read and write control signals.
3. A flash memory according to claim 2 wherein the global row decoder circuit is configured to activate the first and second local row decoder circuits using the separate read and write control signals.
4. A flash memory according to claim 2 wherein the global row decoder circuit comprises:
a read address decoder circuit configured to activate the read control signal coupled to the first and second separate banks based on a read address provided thereto; and
a write address decoder circuit configured to activate the write control signal coupled to the first and second separate banks based on a write address provided thereto.
5. A flash memory according to claim 1 wherein the local row decoder circuit and the global row decoder circuit are spaced apart within the flash memory.
6. A flash memory according to claim 1 wherein the local row decoder circuit comprises first and second bank select circuits configured to pass the separate read and write control signals to a plurality of word line drivers coupled to a sector within the bank.
7. A flash memory according to claim 6 wherein the first and second bank select circuits comprise at least one totem-pole arrangement of first and second transistors wherein the first and second transistors are conductive to pass at least one of the separate read and write control signals to the plurality of word line drivers associated with the sector responsive to at least one select signal that indicates the local row decoder circuit is coupled to the bank that includes a memory location corresponding to a write or read address provided to the global decoder circuit.
8. A flash memory according to claim 6 wherein the first and second bank select circuits comprise at least one pass transistor configured to pass at least one of the separate read and write control signals to the plurality of word line drivers responsive to at least one bank select signal that indicates that the bank to which the local row decoder circuit is coupled includes a memory location corresponding to an address provided to the flash memory.
9. A flash memory according to claim 1 wherein the global row decoder circuit comprises first and second NAND combinatorial logic circuits or first and second NOR combinatorial logic circuits configured to provide the separate read and write control signals.
10. A flash memory according to claim 9 wherein the first and second NAND combinatorial logic circuits or the first and second NOR combinatorial logic circuits are configured to activate responsive to a read address for a read operation or a write address for a write operation respectively.
11. A flash memory according to claim 1 wherein the bank comprises a first bank, wherein the flash memory has read-while-write capability comprising an ability to perform a write operation in the first bank of the flash memory via the first local row decoder circuit while simultaneously performing a read operation in a second bank of the flash memory via another local row decoder circuit.
12. A flash memory according to claim 1 wherein the flash memory has read-while-write capability comprising an ability to perform a first read or write operation in a first sector of the bank while simultaneously performing a second read or write operation in a second sector of the bank that is separate from the first sector via another local row decoder circuit.
13. A flash memory comprising:
a local row decoder circuit configured to drive word lines coupled to a bank of a flash memory responsive to separate read and write control signals provided thereto from outside the local row decoder circuit, wherein the bank of flash memory comprises a first bank of the flash memory configured to perform a write operation addressed to the first bank via the local row decoder circuit, the flash memory farther comprising:
a second bank of the flash memory configured to perform a read operation addressed thereto via a second local row decoder circuit simultaneous with the write operation.
14. A flash memory having read-while-write capability comprising:
a plurality of banks of a flash memory;
a plurality of local row decoder circuits configured to drive a plurality of word lines coupled to a respective sector in each of the plurality of banks; and
a global row decoder circuit configured to provide separate write and read control signals to each of the plurality of local row decoder circuits to enable a read operation in a first sector in one of the plurality of banks and enable a write operation in a second sector in another of the plurality of banks simultaneous with the read operation.
15. A flash memory according to claim 14 wherein the global row decoder circuit is coupled to the plurality of local row decoder circuits via the separate read and write control signals, and configured to determine whether to activate the separate read and write control signals based on an address for the read or write operation provided to the global row decoder circuit.
16. A flash memory according to claim 15 wherein the global row decoder circuit comprises:
a read address decoder circuit configured to activate the read control signal coupled to the first and second separate banks based on a read address provided thereto; and
a write address decoder circuit configured to activate the write control signal coupled to the first and second separate banks based on a write address provided thereto.
17. A flash memory according to claim 16 wherein the read address decoder circuit and the write address decoder circuit are configured to be active simultaneously.
18. A flash memory according to claim 15 wherein the bank comprises a first bank, wherein the flash memory has read-while-write capability comprising an ability to perform a write operation in the first bank of the flash memory via the first local row decoder circuit while simultaneously performing a read operation in a second bank of the flash memory via another local row decoder circuit.
19. A flash memory according to claim 15 wherein the flash memory has read-while-write capability comprising an ability to perform a first read or write operation in a first sector of the bank while simultaneously performing a second read or write operation in a second sector of the bank that is separate from the first sector via another local row decoder circuit.
20. A flash memory according to claim 14 wherein the plurality of local row decoder circuits and the global row decoder circuit are spaced apart within the flash memory.
21. A flash memory according to claim 20 wherein the global row decoder circuit comprises first and second NAND combinatorial logic circuits or first and second NOR combinatorial logic circuits configured to provide the separate read and write control signals.
22. A flash memory according to claim 21 wherein the first and second NAND combinatorial logic circuits or the first and second NOR combinatorial logic circuits are configured to activate responsive to a read address for a read operation or a write address for a write operation respectively.
23. A flash memory according to claim 14 wherein the local row decoder circuit comprises first and second bank select circuits configured to pass the separate read and write control signals to a plurality of word line drivers coupled to a sector within the bank.
24. A flash memory according to claim 23 wherein the first and second bank select circuits comprise at least one totem-pole arrangement of first and second transistors wherein the first and second transistors are conductive to pass at least one of the separate read and write control signals to the plurality of word line drivers associated with the sector responsive to at least one select signal that indicates the local row decoder circuit is coupled to the bank that includes a memory location corresponding to a write or read address provided to the global decoder circuit.
25. A flash memory according to claim 23 wherein the first and second bank select circuits comprise at least one pass transistor configured to pass at least one of the separate read and write control signals to the plurality of word line drivers responsive to at least one bank select signal that indicates that the bank to which the local row decoder circuit is coupled includes a memory location corresponding to an address provided to the flash memory.
26. A flash memory according to claim 14 wherein the bank of flash memory comprises a first bank of the flash memory configured to perform a write operation addressed to the first bank via the local row decoder circuit, the flash memory further comprising:
a second bank of the flash memory configured to perform a read operation addressed thereto via a second local row decoder circuit simultaneous with the write operation.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A roller blind control mechanism for raising and lowering a fabric blind, the fabric blind having a bottom bar mounted to a lower edge of the fabric blind, the control mechanism comprising;
a. An elongated roller tube for winding up the fabric blind;
b. An elongated housing for containing the roller tube within an elongated chamber, the elongated housing having a top wall and first and second walls depending from the top wall, the first, second and top walls enclosing the elongated chamber, the housing having a lower opening extending between the roller tube and the second wall through which the fabric blind passes;
c. A stopper for blocking the bottom bar from entering the elongated chamber, the stopper having a head portion, a toe portion and a neck portion connecting the head and toe portions, the head portion mounted to the top wall of the housing adjacent the second wall, the neck portion being dimensioned and configured such that the toe portion extends downwardly and is positioned in the lower opening, the toe portion being dimensioned and configured to block passage of the bottom bar between the roller tube and the second wall;
d. The toe portion having a multi-position spacer element for positioning the toe portion between proximate and distal positions relative to the second wall.
2. A roller blind control system as defined in claim 1 wherein the second wall has an edge adjacent the lower opening, the multi-position spacer comprising a plurality of grooves formed on the toe portion, each of the grooves configured to engage said edge.
3. A roller blind control system as defined in claim 1 wherein the neck portion of the stopper is sufficiently flexible and resilient such that the toe portion is biased towards its proximate position.
4. A roller blind control system as defined in claim 2 wherein the neck portion of the stopper is sufficiently flexible and resilient such that the toe portion is biased towards its proximate position.
5. A roller blind control system as defined in claim 4 wherein the stopper is made of a resilient plastic and wherein a flexible joint is formed on the neck between the toe and head portions, the flexible joint comprising a thinning of the neck.
6. A roller blind control system as defined in claim 1 wherein the housing includes a mounting cavity formed on the top wall of the housing adjacent the second wall, the mounting cavity and the head portion of the stopper being dimensioned and configured such that the head portion of the stopper fits within the mounting cavity, the mounting cavity having a bottom opening through which the neck of the stopper can pass through.
7. The roller blind control system as defined in claim 6 wherein a resilient spring is formed on the head portion of the stopper, the resilient spring configured to firmly hold the head portion of the stopper within the mounting cavity.
8. The roller blind control system as defined in claim 7 wherein the resilient spring comprises a resilient spring member formed on the head portion, the resilient spring member movable between a retracted position wherein the spring member lies flat against the rest of the head portion to enable the head portion to fit easily within the mounting cavity, and an extended portion wherein the arm extends away from the rest of the head portion, the arm being biased towards its extended position.
9. A roller blind control mechanism for raising and lowering a fabric blind, the fabric blind having a bottom bar mounted to a lower edge of the fabric blind, the control mechanism comprising;
a. An elongated roller tube for winding up the fabric blind;
b. An elongated housing for containing the roller tube within an elongated chamber, the elongated housing having a front fascia, a top wall, and a back wall enclosing the elongated chamber, the housing having a lower opening for allowing the blind to pass there through, the lower opening positioned between the roller tube and the back wall;
c. A stopper for blocking the bottom bar from entering the elongated chamber, the stopper having a head portion, a toe portion and a neck portion connecting the head and toe portions, the head portion mounted to the housing adjacent the back wall, the neck portion being dimensioned and configured such that the toe portion extends downwardly and is positioned in the rearward portion of the lower opening, the toe portion being dimensioned and configured to block passage of the bottom bar between the roller tube and the back wall;
d. The toe portion having a multi-position spacer element for selectively positioning the toe portion between proximate and distal positions relative to the back wall.
10. The roller blind control mechanism as defined in claim 9 wherein the multi-position spacer element comprises a plurality of grooves formed on the toe portion, the grooves each being configured to mount to an edge of the back wall.