1. A video apparatus, comprising:
a recorder configured to record a video content including caption information;
a setting register configured to set search parameters including a keyword; and
a chapter generator configured to extract chapters each including an interval in which the keyword appears in a caption or captions from the video content, by
setting a start point of a period in which a caption containing the keyword is to be displayed first as a chapter start point, and
setting a point that comes first after the end of display of a tail caption containing the keyword among a point when a silent interval starts, a point when a prescribed time elapses, and an end point of a packet concerned of the video content consisting of plural packets as a chapter end point.
2. The video apparatus of claim 1, further comprising:
a play list generator configured to generate a play list by combining the plural chapters extracted by the chapter generator.
3. The video apparatus of claim 2,
wherein the search parameters include at least one of a video content recording period, a genre and a provider.
4. The video apparatus of claim 3, further comprising:
a keyword extractor configured to analyze the caption information of the video content and to extract, as keyword candidates, words or phrases that appear at high frequencies,
wherein the keyword is set from among the keyword candidates through the setting register.
5. A video apparatus control method, comprising:
recording a video content including caption information into a recorder;
setting search parameters including a keyword through a setting register; and
extracting chapters each including an interval in which the keyword appears in a caption or captions from the video content using a chapter generator, by
setting a start point of a period in which a caption containing the keyword is to be displayed first as a chapter start point, and setting a point that comes first after the end of display of a tail caption containing the keyword among a point when a silent interval starts, a point when a prescribed time elapses, and an end point of a packet concerned of the video content consisting of plural packets as a chapter end point.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A cell for an arithmetic logic unit comprising a mirror adder circuit modified to perform additional arithmetic or logic functions without additional transistors excluding input or output inverters, comprising:
a first masked input a*;
a second masked input b*;
a third masked input ci*, wherein the third masked input ci* is a masked carry input, a mask bit kp, or an inverted mask bit kp;
a first control input xe0 and a second control input xe1; and
a first circuit comprising a first plurality of transistors, wherein inputs of the first plurality of transistors are connected to the first masked input a*, the second masked input b*, and the third masked input ci*, and the first plurality of transistors having a first output co*_n, the first output co*_n being a masked inverted carry-out bit;
a second circuit comprising a second plurality of transistors, wherein inputs of the second plurality of transistors are connected to the first masked input a*, the second masked input b*, the first output co*_n, the first control input xe0, and the second control input xe1, and the second plurality of transistors having a second output s*_n;
the second output s*_n having a first value, when the first control input xe0, the second control input xe1, and the third masked input ci* are equal to the masked carry input, the first value being an inverted masked sum bit s*_n of a masked addition of the first masked input a*, the second masked input b*, and the third masked input ci*;
the second output s*_n having a second value when the first control input xe0, the second control input xe1, and the third masked input ci* are equal to the mask bit kp, the second value being an inverted masked XOR output of the first masked input a* and the second masked input b*,
the second output s*_n having a third value when the first control input xe0, the second control input xe1, and the third masked input ci* are equal to the inverted mask bit kp, the third value being an inverted masked XNOR output of the first masked input a* and the second masked input b*; and
the second output s*_n having a fourth value when the values at the first control input xe0 and the second control input xe1 are independent of the value at the third masked input ci*, the fourth value being an inverted masked NAND or NOR output of the first masked input a* and the second masked input b*.
2. The cell as recited in claim 1 wherein the second output s*_n having the fourth value when the first control input xe0 is a logical zero and the second control input xe1 a logical one.
3. The cell as recited in claim 1 further comprising:
a NAND gate having a carry bit output co*p based on a control bit input m1 and the masked inverted carry-out bit co*_n.
4. A processor comprising a plurality of cells as recited in claim 1.
5. The cell as recited in claim 1, further comprising:
a second mask bit kp\u22121;
a carry bit input ci’;
three control bit inputs m1, m2, m3; and
a third circuit outputting the third masked input ci* to the first circuit and the first control input xe0, and the second control input xe1 to the second circuit.
6. The cell as recited in claim 1, further comprising:
an upstream mask bit input kp\u22121 inputting the mask bit from an immediately upstream ALU cell;
a carry bit input ci’; and
a third circuit outputting the third masked input ci* to the first circuit and outputting the first control input xe0 and the second control input xe1 to the second circuit as a function of the mask bit kp and the upstream mask bit input kp\u22121.
7. The cell as recited in claim 6 further comprising three control bit inputs m1, m2, m3.
8. The cell as recited in claim 1, further comprising:
a carry bit input ci’;
a second mask but input kp\u22121;
a control circuit receiving the carry bit input ci’ and the mask bit kp, the second mask bit input kp\u22121, and outputting the third masked input ci*, the control circuit having at least three control states; and
the second circuit logically combining the first masked input a*, the second masked input b* and the third masked input ci* to: (a) arithmetically masked add the first masked input a*, the second masked input b* and the third masked input ci* when the control circuit is in a first of the three control states, (b) masked XOR or XNOR the first masked input a* and second masked input b* when the control circuit is in a second state of the three control states; and (c) masked NOR or NAND the first masked input a* and second masked input b* when the control circuit is in a third state of the three control states.
9. A method for logically combining two masked inputs a* and b* in a masked ALU cell comprising a mirror adder circuit modified to perform additional arithmetic or logic functions without additional transistors excluding input or output inverters comprising:
providing a first circuit;
providing a second circuit to mask a carry bit ci’ received from an adjacent upstream ALU cell by performing an exclusive-or operation on the carry bit ci’ with a first mask bit kp and a second mask bit kp-1, the second circuit outputting a masked input ci*, wherein the masked input ci* is a masked carry input, the first mask bit kp, or an inverted mask bit kp ;
controlling the first circuit by the second circuit through two control signals xe0 and xe1 and the masked input ci*, in order for the first circuit to arithmetically masked add two masked inputs a*, b*, and the masked input ci* when the two control signals xe0 and xe1 and the masked input ci* are equal to the masked carry input;
perform bitwise inverted masked XOR operation on the two masked inputs a*, b* when the two control signals xe0 and xe1 and the masked input ci* are equal to the mask bit kp; and
perform bitwise inverted masked XNOR operation on the two masked inputs a*, b* when the two control signals xe0 and xe1 and the masked input ci* are equal to the inverted mask bit kp; and
perform bitwise inverted masked NAND or NOR operation on the two masked inputs a*, b* when the two control signals xe0 and xe1 are independent of the masked input ci*.
10. A processing unit comprising a mirror adder circuit modified to perform additional arithmetic or logic functions without additional transistors excluding input or output inverters comprising:
a control unit adapted to generate a remasked input ci*, a first control input xe0, and a second control input xe1 wherein the remasked input ci* is a masked carry input, a mask bit kp, or an inverted mask bit kp; and
a data unit adapted to generate a masked inverted carry output co*_n based on the remasked input ci* using a first set of transistors, and a masked inverted sum bit s*_n based on the first control input xe0, and the second control input xe1 using a second set of transistors, wherein the masked inverted sum bit s*_n is generated from a masked addition of two masked inputs a*, b* and the remasked input ci* when the first control input xe0, the second control input xe1 and the remasked input ci* are equal to the masked carry input; and
wherein the masked inverted sum bit s*_n is generated from a bitwise inverted masked XOR of the two masked inputs a*, b* when the first control input xe0, the second control input xe1 and the remasked input ci* are equal to the mask bit kp; and
wherein the masked inverted sum bit s*_n is generated from a bitwise inverted masked XNOR of the two masked inputs a*, b* when the first control input xe0, the second control input xe1 and the remasked input ci* are equal to the inverted mask bit kp; and
wherein the masked inverted sum bit s*_n is generated from a bitwise inverted masked NAND or NOR of the two masked inputs a*, b* when the first control input xe0 and the second control input xe1 are independent of the remasked input ci*.
11. The processing unit of claim 10, wherein the control unit is adapted to generate the remasked input ci* from a first function of a masked carry bit input ci’, the mask bit kp, and a second function.
12. The processing unit of claim 11, wherein the second function is a function of first control bit input m1, a second control bit input m2, and a second mask input kp\u22121.
13. The processing unit of claim 12, wherein the control unit is adapted to generate the first control input xe0 and the second control input xe1 from the first function and a third control bit input m3.
14. The processing unit of claim 10, wherein the data unit is adapted to generate the masked inverted carry output co*_n from the two masked input a*, b*, and the remasked input ci*.
15. The processing unit of claim 14, wherein the two masked input a*, b*, the remasked bit input ci*, the masked carry output co*_n, and the masked inverted sum bit s*_n share the masked bit kp.