1. An ESD protective circuit comprising:
a contact terminal;
a first supply voltage terminal for a first supply potential;
a second supply voltage terminal for a second supply potential;
a transistor chain comprising a plurality of transistors each having a drain terminal, a control terminal and a source terminal, wherein the drain terminals of the transistors are coupled to on of the first or the second supply voltage terminals, wherein the control terminal of a first transistor of the transistor chain is coupled to the other one of the first or second supply voltage terminals, wherein the control terminals of the remaining transistors are each coupled to the source terminal of the previous transistor, and wherein the source terminal of the last transistor of the transistor chain is coupled to the contact terminal; and
a current source coupled to the source terminal of at least one of the transistors of the transistor chain and is able to provide a current that compensates, up to a maximum tolerable voltage deviation from the first or the second supply potential at the contact terminal, a current flowing into or from the source terminal.
2. The ESD protective circuit according to claim 1, wherein the first supply potential is higher than the second supply potential, wherein the transistors of the transistor chain are n-p-n bipolar transistors such that the drain terminal is a collector terminal, the control terminal is a base terminal and the source terminal is an emitter terminal, wherein the collector terminals of the n-p-n transistors are coupled to the first supply potential terminal, wherein the base terminal of the first transistor of the transistor chain is coupled to the second supply voltage terminal, wherein the base terminals of the one or several remaining n-p-n transistors are each coupled to the emitter terminals of the previous transistors, and wherein the emitter terminal of the last transistor is coupled to the contact terminal.
3. The ESD protective circuit according to claim 2, wherein the current source includes a current reducing circuit that is coupled between the supply voltage terminals and is able to generate a voltage lower compared to the second supply potential.
4. The ESD protective circuit according to claim 3, wherein the voltage reducing circuit includes a charge pump.
5. The ESD protective circuit according to claim 1, wherein the first supply potential is higher than the second supply potential, wherein the transistors of the transistor chain are p-n-p bipolar transistors such that the drain terminal is a collector terminal, the control terminal is a base terminal and the source terminal is an emitter terminal, wherein the collector terminals of the p-n-p transistors are coupled to the second supply potential terminal, wherein the base terminal of the first p-n-p transistor of the transistor chain is coupled to the first supply voltage terminal, wherein the base terminals of the one or several remaining p-n-p transistors are each coupled to the emitter terminal of the previous p-n-p transistor, and wherein the emitter terminal of the last p-n-p transistor is coupled to the contact terminal.
6. The ESD protective circuit according to claim 5, wherein the current source includes a current increasing circuit that is coupled between the supply voltage terminals and is able to generate a voltage higher compared to the first supply voltage.
7. The ESD protective circuit according to claim 6, wherein the voltage increasing circuit includes a charge pump.
8. The ESD protective circuit according to claim 1, wherein the current source is coupled to the source terminals of all the transistors of the transistor chain.
9. The ESD protective circuit according to claim 1, wherein the circuit is manufactured in a CMOS technology.
10. A device for ESD protection, comprising:
means for inputting andor outputting a signal;
means for providing a first supply voltage;
means for providing a second supply voltage;
means for switching which comprises several transistors connected in series, wherein drain terminals of the transistors are connected to one of the supply voltages, wherein a control terminal of a first transistor of the means is connected to another one of the supply voltages, wherein control terminals of the one or several remaining transistors are each connected to a source terminal of the previous transistor, and wherein a source terminal of a last transistor of the means is connected to an input andor output contact; and
means for providing a current which is connected to a source terminal of one of the several transistors of the means and is able to provide a current which compensates, up to a maximum tolerable voltage deviation from the first or the second supply voltage at the input andor output contact, a current flowing into or from the source terminal.
11. The device according to claim 10, wherein the transistors of the means are n-p-n bipolar transistors, wherein collector terminals of the n-p-n transistor are connected to the first supply voltage, wherein a base terminal of the first n-p-n transistor of the means is connected to the second supply voltage, wherein the base terminals of the one or several remaining n-p-n transistors are each connected to an emitter terminal of the previous n-p-n transistors, and wherein an emitter terminal of the last n-p-n transistor is connected to the means for providing the input andor output contact.
12. The device according to claim 11, wherein the means for providing a current includes means for reducing a voltage which is connected between the supply voltages and is able to generate a voltage lower compared to the second supply voltage.
13. The device according to claim 12, wherein the means for reducing the voltage includes a charge pump.
14. The device according to claim 10, wherein the transistors of the means are p-n-p bipolar transistors, wherein collector terminals of the p-n-p transistors are connected to the second supply voltage, wherein a base terminal of the first p-n-p transistor of the means is connected to the first supply voltage, wherein base terminals of the one or several remaining p-n-p transistors are each connected to an emitter terminal of the previous p-n-p transistor, and wherein an emitter terminal of the last p-n-p transistor is connected to the means for providing the input andor output contact.
15. The device according to claim 14, wherein the means for providing a current includes means for increasing a voltage which is connected between the supply voltages and is able to generate a voltage higher compared to the first supply voltage.
16. The device according to claim 15, wherein the means for increasing a voltage includes a charge pump.
17. A method for ESD protection, the method comprising:
providing an input andor output contact;
providing a first supply voltage;
providing a second supply voltage;
establishing a connection between the input andor output contact and a terminal for one of the two supply voltages by means of a transistor chain when a maximum tolerable voltage deviation from the first supply potential or the second supply potential is exceeded, wherein the transistor chain comprises several transistors, wherein drain terminals of the transistors are connected to one of the supply voltages, wherein a control terminal of a first transistor of the transistor chain is connected to another one of the supply voltages, wherein control terminals of the one or several remaining transistors are each connected to a source terminal of the previous transistor, and wherein a source terminal of a last transistor of the transistor chain is connected to the input andor output contact; and
providing a current by a current source which is connected to a source terminal of one of the several transistors of the transistor chains and is able to provide a current which compensates, up to a maximum tolerable voltage deviation from the first or the second supply voltage at an input andor output contact, a current flowing into or from the source terminal.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A transition duct for a gas turbine comprising:
a tubular body having a forward end and an aft end;
a plurality of cooling channels formed on an exterior surface of said tubular body at said aft end;
a closure band surrounding said aft end, covering at least a portion of said plurality of cooling channels; and
a seal attached to said closure band, surrounding said aft end of said tubular body.
2. The transition duct of claim 1 wherein said plurality of cooling channels are formed with inlet ends and outlet ends, said outlet ends located at an aft edge of said transition duct.
3. The transition duct of claim 2 wherein said inlet ends comprise tapered surface portions that are not covered by said closure band.
4. The transition duct of claim 1 wherein said closure band is formed with a plurality of cooling apertures overlying one or more of said plurality of cooling channels.
5. The transition duct of claim 4 wherein at least one of said plurality of cooling apertures is provided for each of said plurality of cooling channels.
6. The transition duct of claim 1 wherein means are provided within said plurality of cooling channels for enhancing heat transfer.
7. The transition duct of claim 1 wherein said seal is selected from a group comprising brush seals, leaf seals, cloth seals, rope seals and hula seals.
8. The transition duct of claim 1 wherein said seal comprises a brush seal.
9. A method of providing cooling air to an aft end of a gas turbine transition duct comprising:
forming plural open cooling channels on an exterior surface of said transition duct at said aft end thereof, said plural cooling channels extending from an aft edge of said duct in an upstream direction;
closing at least a portion of said plural open cooling channels with a peripheral closure band to thereby form cooling passageways; and
incorporating a seal into said closure band.
10. The method of claim 9 wherein said cooling channels have substantially rectangular cross-sectional shapes.
11. The method of claim 9 wherein said seal is chosen from a group comprising brush seals, leaf seals, cloth seals, rope seals and hula seals.
12. The method of claim 9 including forming said plural open cooling channels with include tapered inlets.
13. The method of claim 12 wherein said peripheral closure band does not enclose said tapered inlets.
14. The method of claim 9 including forming said plural open cooling channels are with means for enhancing heat transfer.
15. The method of claim 9 wherein including forming said closure band with plural cooling apertures overlying one or more of said plural open cooling channels.