1-23. (canceled)
24. A solid-state imaging device comprising:
a plurality of pixels each of which is two-dimensionally arranged on a semiconductor substrate and comprises a photoelectric conversion portion for converting a light signal to signal charge, an output portion for outputting a signal charge of the photoelectric conversion portion after amplification, and an initializing portion for discharging the signal charge of the photoelectric conversion portion; and
a scanning section for selectively outputting a drive signal to each of the plurality of pixels,
wherein during an operation of reading signals from pixels included in a first pixel group of the plurality of pixels and thinning signals from pixels included in a second pixel group, the initializing portion discharges a signal charge of a photoelectric conversion portion of one of the pixels included in the second pixel group until the signal charge reaches a certain level different from an initial state of a signal charge of a photoelectric conversion portion of one of the pixels included in the first pixel group.
25. The solid-state imaging device of claim 24, wherein a period of time to initialize the photoelectric conversion portion of the pixel included in the second pixel group is a shortest period of time determined by a reference clock.
26. The solid-state imaging device of claim 24, wherein a drive voltage applied to the initializing portion to initialize the photoelectric conversion portion of the pixel included in the second pixel group is lower than a drive voltage applied to the initializing portion to initialize the photoelectric conversion portion of the pixel included in the first pixel group.
27. The solid-state imaging device of claim 24, wherein a drain voltage applied to the initializing portion to initialize the photoelectric conversion portion of the pixel included in the second pixel group is lower than a drain voltage applied to the initializing portion to initialize the photoelectric conversion portion of the pixel included in the first pixel group.
28. The solid-state imaging device of claim 24, further comprising a holding means for holding a drive signal for initializing the photoelectric conversion portion of the pixel included in the second pixel group for a certain period of time.
29. The solid-state imaging device of claim 28, wherein a drive voltage applied to the initializing portion to initialize the photoelectric conversion portion of the pixel included in the second pixel group is lower than a drive voltage applied to the initializing portion to initialize the photoelectric conversion portion of the pixel included in the first pixel group.
30. An imaging apparatus comprising:
the solid-state imaging device of claim 24;
an optical system for allowing light to be incident to the solid-state imaging device;
a control section for outputting a control signal for controlling operation of the solid-state imaging device; and
a signal processing circuit for processing an output signal from the solid-state imaging device and outputting the results as moving picture data or still picture data.
31. The imaging apparatus of claim 30, further comprising a shutter for shutting light from being incident to the solid-state imaging device.
32. The imaging apparatus of claim 30, further comprising a monitor screen for monitoring the data.
33. The imaging apparatus of claim 30, wherein at least one of the control section and the signal processing circuit is placed inside the solid-state imaging device.
34. The solid-state imaging device of claim 24, wherein the scanning section drives the pixels in the first pixel group to perform electronic shutter operation for limiting the time during which the photoelectric conversion element of each of the pixels in the first pixel group accumulates the signal charge, and when one of the pixels in the first pixel group performs the electronic shutter operation, the scanning section drives a pixel from the second pixel group at least adjacent to the one pixel from the first pixel group among the pixels of the second pixel group to perform the discharge operation.
35. The solid-state imaging device of claim 24, wherein the scanning section drives the pixels in the first pixel group to perform electronic shutter operation for limiting the time during which the photoelectric conversion element of each of the pixels in the first pixel group accumulates the signal charge, and when the pixels in the first pixel group lined in one row among the plurality of pixels in the first pixel group perform the electronic shutter operation, the scanning section drives the pixels in the second pixel group lined in a row at least adjacent to the pixels in the first pixel group lined in the one row among the plurality of pixels in the second pixel group to perform the discharge operation.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of programming a memory cell, the method comprising:
performing a first programming operation on the memory cell and applying a first ramped read voltage having a first voltage range to verify programming of the memory cell to a first programmed state corresponding to a target count value while the first ramped read voltage is ramped over the first voltage range; and
performing a second programming operation on the memory cell and applying a second ramped read voltage having a second voltage range to verify programming of the memory cell to a second programmed state corresponding to the target count value while the second ramped read voltage is ramped over the second voltage range;
wherein the first voltage range is different than the second voltage range.
2. The method of claim 1, further comprising receiving a target count value representative of a target programmed state of the memory cell.
3. A method of programming a memory cell of a memory device, the method comprising:
applying a first programming pulse to a memory cell;
applying a first ramped voltage to the memory cell to determine a programmed state of the memory cell while the first ramped voltage is ramped over a first voltage range;
applying a second programming pulse to the memory cell; and
applying a second ramped voltage to the memory cell following the second programming pulse to determine the programmed state of the memory cell while the second ramped voltage is ramped over a second voltage range;
wherein at least one of a minimum voltage or a maximum voltage of the second ramped voltage is different than a respective one of a minimum voltage andor a maximum voltage of the first ramped voltage.
4. The method of claim 3, wherein the minimum voltage of the first ramped voltage is selected to at least partially compensate for coupling effects caused when programming pulses are applied to one or more adjacent memory cells of the memory device subsequent to applying the first programming pulse and prior to applying the second programming pulse.
5. The method of claim 3, wherein applying the second ramped voltage further comprises applying the second ramped voltage where a maximum voltage of the second ramped voltage is greater than a maximum voltage of the first ramped voltage.
6. The method of claim 3, wherein applying the first ramped voltage further comprises applying the first ramped voltage to detect a threshold voltage of the memory cell and determining if the threshold voltage of the memory cell is equal to or exceeds a first particular threshold voltage.
7. The method of claim 6, wherein applying the second programming pulse to the memory cell further comprises applying the second programming pulse to the memory cell to change a threshold voltage of the memory cell in response to the threshold voltage being equal to or exceeding the first particular threshold voltage.
8. The method of claim 6, wherein applying the second ramped voltage further comprises applying the second ramped voltage to detect a threshold voltage of the memory cell and determining if the threshold voltage of the memory cell is equal to or exceeds a second particular threshold voltage.
9. The method of claim 3, further comprising loading a data value into the memory device where the data value is representative of a target programmed state of the memory cell prior to applying the first programming pulse.
10. The method of claim 3, further comprising loading a register of the memory device with a first data value representative of the minimum voltage of the first ramped voltage prior to applying the first ramped voltage to the word line.
11. The method of claim 10, further comprising loading the register of the memory device with a second data value representative of the minimum voltage of the second ramped voltage prior to applying the second ramped voltage to the word line.
12. A method of programming a memory cell of a memory device, the method comprising:
applying a first programming pulse to a memory cell;
applying a first ramped voltage to the memory cell to determine a programmed state of the memory cell;
applying a second programming pulse to the memory cell; and
applying a second ramped voltage to the memory cell following the second programming pulse to determine the programmed state of the memory cell;
wherein at least one of a minimum voltage or a maximum voltage of the second ramped voltage is different than a respective one of a minimum voltage andor a maximum voltage of the first ramped voltage;
wherein a difference between the minimum voltage of the second ramped voltage and a maximum voltage of the second ramped voltage is equal to a difference between the minimum voltage of the first ramped voltage and a maximum voltage of the first ramped voltage.
13. A method of programming a memory cell, the method comprising:
performing a first programming operation wherein the first programming operation comprises applying one or more programming pulses to the memory cell and performing a first verify operation over a first range of voltages following each applied programming pulse where the first range of voltages has a minimum and maximum value; and
performing a second programming operation wherein the second programming operation comprises applying one or more programming pulses to the memory cell and performing a second verify operation over a second range of voltages following each applied programming pulse where the second range of voltages has a minimum and a maximum value; and
wherein at least one of the minimum value or the maximum value of the first range is different from a respective one of the minimum value andor the maximum value of the second range of threshold voltages.
14. The method of claim 13, wherein performing the first programming operation and performing the second programming operation further comprises performing the second programming operation subsequent to performing the first programming operation.
15. The method of claim 14, further comprising performing the first programming operation and the second programming operation wherein the minimum value of the second range of threshold voltages is greater than the minimum value of the first range of threshold voltages.
16. The method of claim 14, further comprising performing the first programming operation and the second programming operation wherein the maximum value of the second range of threshold voltages is greater than the maximum value of the first range of threshold voltages.
17. The method of claim 14, further comprising performing the first programming operation and the second programming operation wherein the minimum value of the second range of threshold voltages is greater than the minimum value of the first range of threshold voltages and wherein the maximum value of the second range of threshold voltages is greater than the maximum value of the first range of threshold voltages.
18. The method of claim 13, wherein the first range of voltages is selected to at least partially compensate for coupling effects resulting from subsequent programming operations performed on adjacent memory cells.
19. A method of programming a memory cell of a memory device, the method comprising:
programming a selected memory cell to a partially programmed state and verifying the selected memory cell to the partially programmed state by applying a first ramped voltage to the memory cell where the first ramped voltage has a minimum voltage and a maximum voltage;
performing a programming operation on one or more memory cells adjacent to the selected memory cell; and
programming the selected memory cell to a final programmed state and verifying the selected memory cell to the final programmed state by applying a second ramped voltage to the memory cell where the second ramped voltage has a minimum voltage and a maximum voltage;
wherein the minimum voltage of the second ramped voltage is greater than the minimum voltage of the first ramped voltage; and
wherein the maximum voltage of the second ramped voltage is greater than the maximum voltage of the first ramped voltage.