1. An external storage control device which receives a command from a host system and transfers data to and from an external storage device, comprising:
a detecting section which detects a write command for writing data from said host system to a task file register in said external storage control device, when in a power-saving mode during which a clock from an oscillator is not supplied to said external storage control device; and
a latch section which stores said data in synchronism with said write command.
2. An external storage control device which receives a command from a host system and transfers data to and from an external storage device, comprising:
a first latch section which stores data received from said host system for writing to a task file register in said external storage control device, when in a normal power mode during which a clock is supplied from an oscillator to said external storage control device;
a second latch section which stores data received from said host system for writing to said task file register in said external storage control device, when in a power-saving mode during which the clock from said oscillator is not supplied to said external storage control device; and
a selecting section which selects the data to be written to said task file register in such a manner that, in said normal power mode, the data stored in said first latch section is written to said task file register and, in said power-saving mode, the data stored in said second latch section is written to said task file register.
3. An external storage control device as claimed in claim 1, further comprising a signal generating section which generates a signal for causing the data stored during said power-saving mode to be written to said task file register when clock operation is resumed by switching from said power-saving mode during which the clock from said oscillator is not supplied to said external storage control device back to said normal power mode during which the clock from said oscillator is supplied to said external storage control device.
4. An external storage control device as claimed in claim 2, further comprising a signal generating section which generates a signal for causing the data stored during said power-saving mode to be written to said task file register when clock operation is resumed by switching from said power-saving mode during which the clock from said oscillator is not supplied to said external storage control device back to said normal power mode during which the clock from said oscillator is supplied to said external storage control device.
5. An external storage control device as claimed in claim 3, wherein the data stored during said power-saving mode is written to said task file register when the output signal of said signal generating section is inverted.
6. An external storage control device as claimed in claim 4, wherein the data stored during said power-saving mode is written to said task file register when the output signal of said signal generating section is inverted.
7. A program for use in an external storage control device which receives a command from a host system and transfers data to and from an external storage device, said program causing a computer to execute the steps of:
setting a power-down bit for switching from a normal power mode during which a clock is supplied from an oscillator to said external storage control device to a power-saving mode during which said clock is not supplied;
stopping the supply of said clock from said oscillator to said external storage control device when said power-down bit is set;
when switching is made from said power-saving mode back to said normal power mode, then resetting said power-down bit and writing, to a task file register in said external storage control device, data that has been transferred from said host system for writing to said task file register and that has been held in a latch section while the supply of said clock to said external storage control device is stopped; and
resuming the supply of said clock from said oscillator to said external storage control device when switching has been made from said power-saving mode back to said normal power mode.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of manufacture of an integrated circuit packaging system comprising:
providing a shaped platform with a conductive post;
mounting the shaped platform with the conductive post over a temporary carrier;
mounting an integrated circuit device over the temporary carrier;
encapsulating the conductive post and the integrated circuit device leaving a first end of the conductive post exposed from the encapsulation;
removing a portion of the shaped platform forming at least two discrete conductive post whereby the conductive post extends through the encapsulant and a second end of the conductive post is exposed from the encapsulant; and
removing the temporary carrier.
2. The method as claimed in claim 1 wherein removing the portion of the shaped platform includes providing a top encapsulant surface of an encapsulant coplanar with a contact surface of the conductive posts.
3. The method as claimed in claim 1 further comprising
forming a top connect structure over the integrated circuit, the top connect structure connected with a contact surface of the conductive posts; and
forming a bottom connect structure below the integrated circuit, the bottom connect structure connected with a base surface of the conductive posts.
4. The method as claimed in claim 1 wherein mounting the integrated circuit device includes mounting the integrated circuit device over the temporary carrier adjacent the conductive posts.
5. The method as claimed in claim 1 further comprising stacking a first stackable assembly over a second stackable assembly, a conductive post of the second stackable assembly connects to a conductive post of the first stackable assembly.
6. A method of manufacture of an integrated circuit packaging system comprising:
providing a temporary carrier with an adhesive layer;
mounting a shaped platform with a conductive post on the adhesive layer;
mounting an integrated circuit device with an active side on the adhesive layer adjacent the conductive post;
encapsulating the conductive post and the integrated circuit device leaving a first end of the conductive post exposed from the encapsulation;
removing the shaped platform from the conductive post whereby the conductive post extends through the encapsulant and a second end of the conductive post is exposed from the encapsulant; and
removing the temporary carrier and the adhesive layer.
7. The method as claimed in claim 6 wherein mounting the integrated circuit device includes mounting the integrated circuit device with the active side on the adhesive layer below an access through region adjacent the conductive post and over the temporary carrier.
8. The method as claimed in claim 6 wherein encapsulating the conductive post includes:
applying an encapsulant over the conductive post, the shaped platform, and the integrated circuit device; and
removing a portion of the encapsulant to expose the shaped platform.
9. The method as claimed in claim 6 further comprising forming a bottom connect structure having an integrated passive device layer and a bottom exposed conductor electrically connected to the post and below the conductive post.
10. The method as claimed in claim 6 further comprising forming a top connect structure having a redistribution layer over the conductive post.