1. An arrangement including
a set of knitting machine needles, each having a shaft that is provided with a hook at one end, an opposite end portion provided with a butt, and having planar side surfaces, and,
a needle pouch for the knitting machine needles, comprising
a first strip of flexible material; with a width of the first strip being greater than a width of the needle set and with a length of the first strip being greater than a length of a knitting machine needle,
a second strip of flexible material; with a width of the second strip being greater than a width of the needle set, and with the second strip lying face-to-face on a portion of a flat-disposed first strip, and
at least two strip-shaped connecting regions wherein the second strip is connected to the first strip to form a pouch there between, with the dimensions of the formed pouch being such that the knitting needles of the needle set are clamped together and held in parallel relationship with abutting side surfaces in alignment by the fit of the pouch and with the butt containing opposite end portions of the needles being free to be grasped by hand.
2. The arrangement defined in claim 1, wherein a lid portion of the first strip is folded over the second strip and the pouch andor is releasably secured to at least one of the second strip and to the pouch.
3. The arrangement defined in claim 1, wherein the flexible material from which the first and second strips is made, is paper.
4. The arrangement defined in claim 1, wherein the flexible material from which the first and second strips is made, is a plastic.
5. The arrangement defined in claim 1, wherein the flexible material from which the first and second strips is made, is a laminated material.
6. The arrangement defined in claim 1, wherein the first strip and the second strip constitute a coherent strip and adjoin one another along a fold line.
7. The arrangement defined in claim 1, wherein the first strip and the second strip are regions of one and the same coherent strip.
8. The arrangement defined in claim 6, wherein the fold line extends transversely to the longitudinal direction of the strip from one edge to another edge thereof.
9. The arrangement defined in claim 6, wherein the fold line is parallel to the longitudinal direction of the first strip.
10. The arrangement as defined in claim 1, wherein the connecting regions are adhesive locations.
11. The arrangement as defined in claim 1, wherein the connecting regions are weld locations.
12. The arrangement as defined in claim 1, wherein the connecting regions are crimped locations.
13. The arrangement as defined in claim 1, wherein the connecting regions border the edge of the strip and the pouch is enclosed between the two connecting regions.
14. The arrangement as defined in claim 1, wherein the width of the pouch equals the width of the needle set.
15. The arrangement as defined in claim 1, wherein the length of the pouch equals the length of the needle shanks.
16. The arrangement as defined in claim 1, wherein an adhesive location is provided for releasably securing the lid portion.
17. The arrangement as defined in claim 1, wherein an adhering tab or a seal is provided for releasably securing the lid portion.
18. The arrangement as defined in claim 1, wherein the length of the second strip is less than the length of a knitting machine needle.
19. A needle package comprising a needle pouch as defined in claim 1 and a box for receiving the needle pouch.
20. The needle package as defined in claim 19, wherein the box is a plastic box.
21. The needle package as defined in claim 19, wherein the box has an inner space, whose base outline corresponds to the outer contour of the needle pouch.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A processor comprising:
instructions with at least one operand field, the instructions comprises immediate instructions having immediate data in the operand field;
a data table for storing immediate data, wherein immediate data are stored in the data table in an order determined by a flow analysis, the data table enables immediate data to be separated from the instruction stream;
a program counter for storing an instruction address of an instruction, wherein the processor fetches an instruction from the instruction address in the program counter during program execution;
an instruction decoder for decoding the instruction fetched by the processor, wherein immediate data from the data table is provided to the processor if the instruction fetched is an immediate instruction;
an instruction register coupled to the instruction decoder, the instruction register stores the instruction fetched by the processor during program execution and passes the instruction to the instruction decoder for decoding; and
a data table addressing unit coupled to the data table and the instruction register, the instruction register passing relative addressing information contained in the instruction to the data table addressing unit when the decoder decodes the immediate instruction, the relative addressing information, which comprises an index and a format indicator, is used to provide an address of the immediate data in the data table,
wherein the data addressing unit comprises a data table pointer containing a value,
if the format indicator comprises a post-format, the value serves as the address and after the immediate data is provided to the processor, the index is added to the value to produce a new value in the data table pointer for a next immediate instruction,
if the format indicator comprises a pre-format, the index is added to the value to produce the address to the immediate data and the address is incremented by 1 after the immediate data is provided to the processor to produce a new value in the data table pointer for the next immediate instruction,
the format indicator comprises a binary bit having a logic 1 and logic 0 value, the logic 1 indicating one of pre-format or post-format and the logic 0 indicating other of pre-format or post-format,
the data table addressing unit further comprising,
a first adder comprising a first input coupled to the instruction register for receiving the index and a second input coupled to an output of the data table pointer for receiving the value contained therein,
a second adder comprising a first input coupled to the instruction register for receiving the format indicator, a second input coupled to an output of the first adder, and an output coupled to the data table pointer, and
a multiplexor comprising a first input coupled to an output of the data table pointer, a second input coupled to the output of the first adder, and a select input coupled to the instruction register for receiving the format indicator to select an multiplexor output from the first and second multiplexor inputs.
2. The processor of claim 1 wherein the data table addressing unit comprises an incrementor for incrementing the address after the immediate data is provided to produce a new address for a new immediate instruction.
3. The processor of claim 1 or 2 wherein the flow analysis comprises a static flow analysis, the static flow analysis to identifies immediate instructions within a program.
4. The processor of claim 3 wherein an immediate instruction comprises addressing information to enable the processor to retrieve a corresponding immediate data to the immediate instruction.
5. The processor of claim 4 wherein the addressing information comprises absolute addressing information.
6. The processor of claim 4 wherein the addressing information comprises relative addressing information.
7. A processor comprising:
a data table for storing immediate data of immediate instructions;
a program counter for storing an instruction address of an instruction, wherein the processor fetches the instruction from the instruction address in the program counter during program execution; and
an instruction decoder for decoding the instruction fetched by the processor, wherein immediate data from the data table is provided to the processor if the instruction is an immediate instruction;
an instruction register coupled to the instruction decoder, the instruction register stores the instruction fetched by the processor during program execution and passes the instruction to the instruction decoder for decoding;
a data table addressing unit comprising a data table pointer containing a value, the data table is coupled to the data table and instruction register, the instruction register passing relative addressing information contained in the instruction to the data table addressing unit when the decoder decodes the immediate instruction, the relative addressing information, which comprises an index and a format indicator, is used to provide an address of the immediate data in the data table, wherein the format indicator comprises a binary bit having a logic 1 and logic 0 value, the logic 1 indicating one of a pre-format or a post-format and the logic 0 indicating other of the pre-format or post-format;
if the format indicator indicates the post-format, the value serves as the address and after the immediate data is provided to the processor, the index is added to the value to produce a new value in the data table pointer for a next immediate instruction and if the format indicator indicates the pre-format, the index is added to the value to produce the address to the immediate data and the address is incremented by 1 after the immediate data is provided to the processor to produce a new value in the data table pointer for the next immediate instruction; and
wherein the addressing unit comprises
a first adder comprising a first input coupled to the instruction register for receiving the index and a second input coupled to an output of the data table pointer for receiving the value contained therein,
a second adder comprising a first input coupled to the instruction register for receiving the format indicator, a second input coupled to an output of the first adder, and an output coupled to the data table pointer, and
a multiplexor comprising a first input coupled to an output of the data table pointer, a second input coupled to the output of the first adder, and a select input coupled to the instruction register for receiving the format indicator to select an multiplexor output from the first and second multiplexor inputs.
8. A processor comprising:
a data table for storing immediate data of immediate instructions;
a program counter for storing an instruction address of an instruction, wherein the processor fetches the instruction from the instruction address in the program counter during program execution; and
an instruction decoder for decoding the instruction fetched by the processor, wherein immediate data from the data table is provided to the processor if the instruction is an immediate instruction;
an instruction register coupled to the instruction decoder, the instruction register stores the instruction fetched by the processor during program execution and passes the instruction to the instruction decoder for decoding;
a data table addressing unit comprising a data table pointer having a value, the data table addressing unit receives relative addressing information for decoded immediate instructions, the relative addressing information, which comprises an index and a format indicator, is used to provide an address of the immediate data in the data table;
if the format indicator indicates a post-format, the value serves as the address and after the immediate data is provided to the processor, the index is added to the value to produce a new value in the data table pointer for a next immediate instruction and if the format indicator indicates a pre-format, the index is added to the value to produce the address to the immediate data and the address is incremented by 1 after the immediate data is provided to the processor to produce a new value in the data table pointer for the next immediate instruction; and
wherein the addressing unit comprises
a first adder comprising a first input coupled to the instruction register for receiving the offset and a second input coupled to an output of the data table pointer for receiving the value contained therein,
a second adder comprising a first input coupled to the instruction register for receiving the format indicator, a second input coupled to an output of the first adder, and an output coupled to the data table pointer, and
a multiplexor comprising a first input coupled to an output of the data table pointer, a second input coupled to the output of the first adder, and a select input coupled to the instruction register for receiving the format indicator to select an multiplexor output from the first and second multiplexor inputs.