1. An input circuit for a memory device, comprising:
2N data buffers for receiving data applied from an outside;
N input multiplexers; and
2N data bus writers;
wherein a pair of data buffers among the 2N data buffers are connected to one of the N input multiplexers, respectively;
the respective input multiplexer is connected to a pair of data bus writers among the 2N data bus writers; and
a certain pair of the i-th and (i+1)-th data buffers among the 2N data buffers correspond to the k-th input multiplexer and the k-th input multiplexer corresponds to the i-th and (i+1)-th data bus writers; and
wherein (a) if first data and second data are outputted from the i-th and (i+1)-th data buffers, the k-th input multiplexer transfers the first data to the i-th data bus writer, and the second data to the (i+1)-th data bus writer; and
(b) if a third data is outputted from only one of the i-th and (i+1)-th data buffers, the k-th input multiplexer selectively transfers the third data to one of the i-th and (i+1)-th data bus writers, and the k-th input multiplexer operates so that a transfer path of the third data is determined by a one-clock-delayed block column address in comparison to a column address inputted by a write command.
2. The input circuit as claimed in claim 1, wherein in the case of (b), output terminals of the input multiplexer from which the third data is not transferred are kept in the previous states.
3. The input circuit as claimed in claim 1, wherein the operation of the data bus writer is controlled by a control signal generated in synchronization with a clock signal after two clocks after the write command is outputted.
4. The input circuit as claimed in claim 1, wherein the k-th input multiplexer comprises:
a first inverter for receiving a first input selection signal X16;
a second inverter for receiving a control signal Yb;
a first NAND gate for receiving an output signal of the first inverter and the control signal Yb;
a second NAND gate for receiving the output signal of the first inverter and an output signal of the second inverter;
a first switch for connecting an output terminal of the i-th data buffer to a first latch;
a second switch for being controlled by an output signal of the first NAND gate and connecting the first latch to a second latch;
a third switch for being controlled by a second input selection signal X8 and connecting an output terminal of the i-th data buffer to a first node;
a fourth switch for being controlled by the first input selection signal and connecting an output terminal of the (i+1)-th data buffer to the first node;
a third latch for latching data of the first node; and
a fifth switch for being controlled by an output signal of the second NAND gate and connecting the third latch to a fourth latch;
wherein the first switch is always in a turned-on state;
the control signal is the block column address;
in the case that the data is inputted to the i-th and (i+1)-th data buffers, the first input selection signal is enabled to a high level and the second input selection signal is disabled to a low level; and
in the case that the data is inputted to either of the i-th and (i+1)-th data buffers, the first input selection signal is disabled to a low level, the second input selection signal is enabled to a high level, and the data transfer path is determined according to a logic level of the control signal.
5. An input circuit for a memory device, comprising:
a plurality of data buffers for receiving data applied from an outside;
an input multiplexer including a block column address input unit for inputting a block column address that is one-clock-delayed in comparison to a column address, a first switchlatch means, connected to an output path of the first data buffer, for storing and outputting output data of the first data buffer, a second switchlatch means, connected to an output path of the second data buffer, for storing and outputting output data of the second data buffer, and a switch means for connecting the output data of the first data buffer to the output path of the second data buffer;
a first data bus writer connected to a first output terminal of the input multiplexer; and
a second data bus writer connected to a second output terminal of the input multiplexer.
6. The input circuit as claimed in claim 5, wherein the data buffers operate in response to an input of a control signal generated in synchronization with a DQS signal.
7. The input circuit as claimed in claim 5, wherein the block column address input unit comprises:
a first decoding unit for receiving the block column address and a first input selection signal and controlling the first switchlatch means; and
a second decoding unit for receiving the block column address and the first input selection signal and controlling the second switchlatch means.
8. The input circuit as claimed in claim 5, wherein the switch means operates in response to an input of a second input selection signal.
9. The input circuit as claimed in claim 8, wherein the first input selection signal is a signal generated if a data inputoutput structure is of X16, and the second input selection signal is a signal generated if the data inputoutput structure is of X8.
10. The input circuit as claimed in claim 5, wherein the first data bus writer outputs data to a first global input line.
11. The input circuit as claimed in claim 5, wherein the second data bus writer outputs data to a second global input line.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for forming lubricant base oils, comprising:
separating a feedstock into at least a first fraction and a bottoms fraction, a distillation cut point for separating the first fraction and the bottoms fraction being at least 950\xb0 F. (510\xb0 C.);
deasphalting the bottoms fraction to form a deasphalted bottoms fraction and an asphalt product;
extracting the deasphalted bottoms in the presence of an extraction solvent to form a raffinate stream and an extract stream, an aromatics content of the raffinate stream being lower than an aromatics content of the deasphalted bottoms;
dewaxing the raffinate stream in the presence of a dewaxing solvent to form a lubricant base oil product and a waxy product having a wax content of at least 70 wt %;
hydrotreating at least a portion of the waxy product under effective hydrotreating conditions to form a hydrotreated effluent, the effective hydrotreating conditions being effective for conversion of 10 wt % or less of a portion of the waxy product boiling above 700\xb0 F. (371\xb0 C.) to a portion boiling below 700\xb0 F. (371\xb0 C.);
separating the hydrotreated effluent to form at least a liquid hydrotreated effluent;
dewaxing the liquid hydrotreated effluent in the presence of a dewaxing catalyst under effective dewaxing conditions to form a dewaxed effluent, the effective dewaxing conditions being effective for conversion of 10 wt % to 35 wt % of a portion of the hydrotreated effluent boiling above 700\xb0 F. (371\xb0 C.) to a portion boiling below 700\xb0 F. (371\xb0 C.); and
fractionating the dewaxed effluent to form a plurality of lubricant base oil products having a viscosity index of at least 120 and a pour point of \u221212\xb0 C. or less, the plurality of base oil products comprising at least a first base oil product having a lower pour point that a second base oil product, the first base oil product having a higher viscosity at 100\xb0 C. than the second base oil product.
2. The method of claim 1, wherein the first base oil product and the second base oil product have a viscosity index of at least 130.
3. The method of claim 1, wherein the plurality of lubricant base oil products have a pour point of \u221215\xb0 C. or less.
4. The method of claim 1, wherein the waxy product has a T50 boiling point of at least 1050\xb0 F. (566\xb0 C.).
5. The method of claim 1, wherein the first base oil product has a viscosity of at least 7.5 cSt at 100\xb0 C.
6. The method of claim 1, wherein the second base oil product has a viscosity of at least 3.5 cSt at 100\xb0 C.
7. The method of claim 1, wherein the first base oil has a viscosity of at least 12 cSt at 100\xb0 C.
8. The method of claim 1, wherein the plurality of base oils further comprises a third base oil having a viscosity of at least 12 cSt at 100\xb0 C., the third base oil having a viscosity index of at least 130.
9. The method of claim 1, wherein the plurality of base oils are substantially free of haze.
10. The method of claim 1, wherein the amount of conversion during hydrotreating is 8 wt % or less relative to a conversion temperature of 371\xb0 C.
11. A method for forming lubricant base oils, comprising:
providing a waxy feedstock having a T5 boiling point of at least at least 800\xb0 F. (427\xb0 C.), a T50 boiling point of at least 1000\xb0 F. (538\xb0 C.), and a wax content of at least 70 wt %;
hydrotreating the waxy feedstock under effective hydrotreating conditions to form a hydrotreated effluent, the effective hydrotreating conditions being effective for conversion of 8 wt % or less of a portion of the waxy product boiling above 700\xb0 F. (371\xb0 C.) to a portion boiling below 700\xb0 F. (371\xb0 C.);
separating the hydrotreated effluent to form at least a liquid hydrotreated effluent;
dewaxing the liquid hydrotreated effluent in the presence of a dewaxing catalyst under effective dewaxing conditions to form a dewaxed effluent, the effective dewaxing conditions being effective for conversion of 10 wt % to 35 wt % of a portion of the hydrotreated effluent boiling above 700\xb0 F. (371\xb0 C.) to a portion boiling below 700\xb0 F. (371\xb0 C.); and
fractionating the dewaxed effluent to form a plurality of lubricant base oil products having a viscosity index of at least 120 and a pour point of \u221215\xb0 C. or less, the plurality of base oil products comprising at least a first base oil product having a lower pour point that a second base oil product, the first base oil product having a higher viscosity at 100\xb0 C. than the second base oil product, the first base oil product and the second base oil product having a viscosity index of at least 130.
12. The method of claim 11, wherein the waxy feedstock has a T5 boiling point of at least 850\xb0 F. (454\xb0 C.).
13. The method of claim 11, wherein the waxy feedstock has a T50 boiling point of at least 1050\xb0 F. (566\xb0 C.).
14. The method of claim 11, wherein the waxy product or the waxy feedstock has a wax content of at least 75 wt %.
15. The method of claim 11, wherein the first base oil product has a viscosity of at least 7.5 cSt at 100\xb0 C.
16. The method of claim 11, wherein the second base oil product has a viscosity of at least 3.5 cSt at 100\xb0 C.
17. The method of claim 11, wherein a total yield for the plurality of base oils is at least 75 wt % of the liquid hydrotreated effluent.
18. The method of claim 11, wherein the amount of conversion during hydrotreating is 8 wt % or less relative to a conversion temperature of 371\xb0 C.
19. The method of claim 11, wherein the plurality of base oils are substantially free of haze.