1. Rudder for seagoing vessels consisting of a main rudder (20) and a fin (10) forced guided by the main rudder (20), articulated thereon over a vertical piston (15), fin which is provided with a horizontal piston (11), whereby the vertical piston (15) and the horizontal piston (11) are connected with each other over a hinged bolt (14) to a sliding swivel piston articulation (100) and a bearing housing (16) of the vertical piston (15) is fixed on a hull, wherein the vertical piston (15) is supported on the hull by an additional thrust bearing (27).
2. Rudder according to claim 1, wherein the thrust bearing (27) is placed on the side of the hinged bolt (14) which is opposite the vertical piston (15).
3. Rudder according to claim 1, wherein the thrust bearing (27) has a bearing bush (22) with a bush (21) into which an end of the vertical piston (15) projecting over the hinged bolt (14) penetrates.
4. Rudder according to claim 3, wherein the bush (21) has a supporting ring (23) on the side of the thrust bearing (27) turned to the vertical piston (15).
5. Rudder according to claim 3, wherein the bush (21) has a supporting ring (24) on the side of the thrust bearing (27) turned away from the vertical piston (15) which forms a movement stopper for the vertical piston (15).
6. Rudder according to claim 3, wherein the bush (21) is made of bronze.
7. Rudder according to claim 1, wherein the thrust bearing (27) is supported on the hull over a horizontal cross bar (19).
8. Rudder according to claim 7, wherein the horizontal cross bar (18) is connected with a vertical cross bar (26) which is supported on the hull.
9. Rudder according to claim 8, wherein the vertical cross bar (26) is connected over a further horizontal cross bar (19) with the bearing housing (16) of the vertical piston (15).
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated circuit comprising:
one or more processors coupled to an internal bus of the integrated circuit;
a cache memory coupled to the bus to cache data for the integrated circuit;
a plurality of interface circuits to transfer packet and non-packet data, wherein each interface circuit is to operate upon a particular mode of communication to transfer respective packet or non-packet data, in which one or more devices are coupled to respective one of the interface circuits based on respective mode of communication for transfer of respective data; and
a bridge circuit coupled to the plurality of interface circuits and to the bus to transfer data between the interface circuits and the bus, the bridge circuit to maintain cache coherency for data cached in the cache memory for devices operable within the integrated circuit, but cache coherency is not maintained by the bridge circuit for data cached in the cache memory by one or more external devices coupled to the interface circuits, wherein the one or more processors, cache memory, plurality of interface circuits and bridge circuit are constructed on one integrated circuit chip as an integrated system on a chip.
2. The integrated circuit of claim 1 further comprising a memory controller coupled to the bus to control transfer of data between the integrated circuit and an external memory when the external memory is coupled to the integrated circuit.
3. The integrated circuit of claim 1 wherein one of the interface circuits is a HyperTransport compatible interface.
4. The integrated circuit of claim 1 wherein one of the interface circuits is a Peripheral Component Interconnect compatible interface.
5. The integrated circuit of claim 1 wherein one of the interface circuits is a network interface.
6. The integrated circuit of claim 1 wherein one of the interface circuits is a Media Independent Interface compatible interface or a Gigabit Media Independent Interface compatible interface.
7. The integrated circuit of claim 1 wherein one of the interface circuits is a serial interface.
8. The integrated circuit of claim 1 wherein one of the interface circuits is a Personal Computer Memory Card International Association compatible interface.
9. The integrated circuit of claim 1 wherein one of the interface circuits is a system management bus interface.
10. A system on a chip comprising:
one or more processors coupled to an internal bus of an integrated circuit formed on a chip, the chip comprising an integrated system to be used with a variety of communication modes;
a cache memory coupled to the bus to cache data for the integrated circuit;
a memory controller coupled to the bus to control transfer of data between the bus, cache memory and main memory;
a plurality of inputoutput (IO) interface circuits to transfer packet and non-packet data, wherein each IO interface circuit is to operate upon a particular mode of communication to transfer respective packet and non-packet data, in which one or more devices are coupled to respective one of the IO interface circuits based on respective mode of communication for transfer of respective data; and
a bridge circuit coupled to the plurality of IO interface circuits and to the bus to transfer data between the IO interface circuits and the bus, the bridge circuit to maintain cache coherency for data cached in the cache memory for devices operable within the integrated circuit, but cache coherency is not maintained by the bridge circuit for data cached in the cache memory by one or more external devices coupled to the IO interface circuits, wherein the one or more processors, cache memory, memory controller, plurality of IO interface circuits and bridge circuit are constructed on one integrated circuit chip as an integrated system on a chip.
11. The system of claim 10 wherein one of the interface circuits is a HyperTransport compatible interface.
12. The system of claim 10 wherein one of the interface circuits is a Peripheral Component Interconnect compatible interface.
13. The system of claim 10 wherein one of the interface circuits is a network interface.
14. The system of claim 13 wherein the network interface circuit is a Media Independent Interface or a Gigabit Media Independent Interface.
15. The system of claim 10 wherein one of the interface circuits is a serial interface.
16. The system of claim 10 wherein one of the interface circuits is a Personal Computer Memory Card International Association compatible interface.
17. The system of claim 10 wherein one of the interface circuits is a system management bus interface.
18. The system of claim 10 wherein a first interface circuit is a HyperTransport compatible interface, a second interface circuit is a Peripheral Component Interconnect compatible interface and a third interface circuit is a network interface.
19. The system of 18 wherein the bridge circuit is comprised of at least two IO bridges wherein the HyperTransport compatible interface and the Peripheral Component Interconnect compatible interface are coupled to the bus through a first IO bridge and remaining interface circuits are coupled through a second IO bridge.