1. A system configured for complex determination of a user’s busy state and for assigning a do not disturb (DND) filter, comprising:
a first electronic device configured to house a DND recognizer module and further configured to store and execute a plurality of applications operable on the first electronic device;
a second electronic device operably associated via a network with the first electronic device, the second electronic device implementing another DND recognizer module, a DND filter module, and a DND propagator module;
wherein the DND recognizer module housed within the first electronic device is configured to analyze and determine the user’s actions, the DND recognizer module is further configured to transmit the determined user’s action data to the DND filter module also housed within the second electronic device;
wherein the DND filter module is configured to determine whether a particular DND filter is associated with the current busy state of the user and to adjust the DND status provided a DND filter does exist, such busy state being based upon the user’s action data, the DND filter module transmits the DND filter data to the DND propagator housed within the second electronic device; and
wherein the DND propagator module is configured to propagate the DND status to at least one device operably associated with the system provided a DND status exists for the current busy state of the user.
2. The system of claim 1, wherein the plurality of applications and the user’s actions in such applications have assigned particular levels of DND.
3. The system of claim 2, wherein the busy state associated with a particular application and the user’s actions in such applications are set by the user via the user’s calendar event scheduler.
4. A method for complex determination of a user’s busy state and for assigning a do not disturb (DND) filter, comprising:
executing an application;
transmitting a user’s action data;
determining whether a particular DND filter is associated with the current busy state of the user and adjusting the DND status provided a DND filter does exist, such busy state being based upon the user’s action data, the DND filter module transmits the DND filter data to the DND propagator; and
propagating the DND status to at least one tool operably associated with the system provided a DND status exists for the current busy state of the user.
5. The method of claim 4, wherein the plurality of applications and the user’s actions in such applications have assigned particular levels of DND.
6. The method of claim 5, wherein the busy state associated with a particular application and the user’s actions in such applications are set by the user via the user’s calendar event scheduler.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An apparatus comprising:
a first input;
a second input;
a first delay line having a plurality of delay stages coupled together in series, the first delay line to receive the first input;
a second delay line having a plurality of delay stages coupled together in series, the second delay line to receive the second input; and
a plurality of comparators, each having first and second inputs coupled to the first and second delay lines,
wherein multiple delay stages of the first and second delay lines are coupled to provide equally delayed input signals for two comparators, and
wherein each of the comparators is coupled to a unique pair of the delay stages.
2. The apparatus of claim 1, wherein the first and second delay lines have equal number of respective plurality of delay stages.
3. The apparatus of claim 2, wherein each of the delay stages of the first and second delay lines have substantially equal propagation delays.
4. The apparatus of claim 1, wherein a sequence of the delay stages coupled to provide the input signals for the plurality of comparators in the first delay line is in the opposite direction to a sequence of the delay stages coupled to provide the input signals in the second delay line.
5. The apparatus of claim 1, wherein each comparator of the plurality of comparators is coupled to the first and second delay lines such that phase difference in every two consecutive comparators from the plurality of comparators is to increment by one delay stage in the first and second delay lines.
6. The apparatus of claim 1, wherein the plurality of comparators has a middle comparator, the middle comparator having an output which indicates a phase error between the first and second inputs which is substantially zero when the first and second inputs have substantially equal phases.
7. The apparatus of claim 1, wherein the plurality of comparators comprises a plurality of flip-flops.
8. The apparatus of claim 1, wherein the plurality of comparators comprises a plurality of bang-bang phase detectors.
9. A phase locked loop (PLL) comprising:
an oscillator to generate an output clock;
a divider to receive the output clock and to generate a feedback clock;
a time-to-digital converter (TDC) for comparing a reference clock with the feedback clock, the TDC including:
a first input;
a second input;
a first delay line having a plurality of delay stages coupled together in series, the first delay line to receive the first input;
a second delay line having a plurality of delay stages coupled together in series, the second delay line to receive the second input; and
a plurality of comparators, each having first and second inputs coupled to the first and second delay lines,
wherein multiple delay stages of the first and second delay lines are coupled to provide equally delayed input signals for two comparators, and
wherein each of the comparators is coupled to a unique pair of the delay stages; and
a controller to receive output of the TDC and to generate a code indicating direction of change in frequency of the output clock.
10. The PLL of claim 9, wherein the oscillator is a digitally controlled oscillator.
11. The PLL of claim 9 further comprises a loop filter to receive the code and to generate a filtered code for use by the oscillator.
12. The PLL of claim 9, wherein the first and second delay lines have equal number of respective plurality of delay stages.
13. The PLL of claim 12, wherein each of the delay stages of the first and second delay lines have substantially equal propagation delays.
14. The PLL of claim 9, wherein a sequence of the delay stages coupled to provide the input signals for the plurality of comparators in the first delay line is in the opposite direction to a sequence of the delay stages coupled to provide the input signals in the second delay line.
15. The PLL of claim 9, wherein each comparator of the plurality of comparators is coupled to the first and second delay lines such that phase difference in every two consecutive comparators from the plurality of comparators is to increment by one delay stage in the first and second delay lines.
16. The PLL of claim 9, wherein the plurality of comparators has a middle comparator, the middle comparator having an output which indicates a phase error between the first and second inputs which is substantially zero when the first and second inputs have substantially equal phases.
17. The PLL of claim 9, wherein the plurality of comparators are at least one of:
a plurality of flip-flops; or
a plurality of bang-bang phase detectors.
18. A system comprising:
a memory;
a processor coupled to the memory, the processor having a time-to-digital converter comprising:
a first input;
a second input;
a first delay line having a plurality of delay stages coupled together in series, the first delay line to receive the first input;
a second delay line having a plurality of delay stages coupled together in series, the second delay line to receive the second input; and
a plurality of comparators, each having first and second inputs coupled to the first and second delay lines,
wherein multiple delay stages of the first and second delay lines are coupled to provide equally delayed input signals for two comparators, and
wherein each of the comparators is coupled to a unique pair of the delay stages; and
a wireless interface for allowing the processor to communicate with another device.
19. The system of claim 18 further comprises a display unit.
20. The system of claim 18, wherein the first and second delay lines have equal number of respective plurality of delay stages, and wherein each of the delay stages of the first and second delay lines have substantially equal propagation delays.