What is claimed is:
1. A method for providing xDSLPOTS line sharing for multiple subscribers, the method comprising the steps of:
(a) accessing a telephone line supporting POTS services destined to a first subscriber; and
(b) multiplexing xDSL services with said POTS services over said telephone line for delivery to a second subscriber.
2. The method described in claim 1 further comprising the step of:
(c) splitting the xDSL services from the POTS services at a remote location; and
(d) forwarding the POTS services to the first subscriber.
3. The method described in claim 1 further comprising the step of:
(c) splitting the xDSL services from the POTS services at a remote location; and
(d) forwarding the xDSL services to a second subscriber.
4. A system providing POTSxDSL line sharing for multiple subscribers over a single telephone line, the system comprising:
(a) a xDSL interface located at or near a central office for sending to and receiving xDSL signals from a first subscriber;
(b) a POTS interface located at or near the central office for sending to and receiving POTS signals from a second subscriber; and
(c) a splittercoupler for multiplexing both xDSL and POTS signal over a single telephone line and for splitting XDSL and POTS signals received over said telephone line.
5. The system described in claim 4 further comprising:
(d) a splitter located in remote location for separating POTS signals from XDSL signals and for forwarding said POTS signals to the second subscriber.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of predicting a logic soft error rate for a circuit of a given technology, the method comprising:
determining a charge stored on at least one logic node in the circuit;
estimating a logic soft error rate for at least one logic node in the circuit using a database of logic soft error rate data points, wherein the data points in the database give a soft error rate as a function, at least in part, of a technology of the circuit, a type of product, and a charge of the logic node; and
calculating the logic soft error rate of the circuit, wherein the logic soft error rate of the circuit is a function of the logic soft error rate of each logic node.
2. The method of claim 1, wherein the step of calculating the logic soft error rate of the circuit is performed by summing the logic soft error rates of each of the at least one logic node.
3. The method of claim 1, further comprising the step of ranking the at least one logic node according to the logic soft error rate for the at least one logic node.
4. The method of claim 3, further comprising the step of reducing the logic soft error rate for a subset of the at least one logic node, wherein the nodes in the subset are based, at least in part, on the logic soft error rate for the individual nodes in the circuit.
5. The method of claim 4, wherein the subset is composed of nodes with a logic soft error rate above a certain value.
6. The method of claim 4, wherein the subset of nodes is a function of a threshold soft error rate for the circuit.
7. The method of claim 4, wherein the step of reducing the logic soft error rate is accomplished by performing at least one of the following on each of the nodes in the subset of nodes:
decreasing the area of the logic node;
adding additional capacitance to the logic node; and
placing a deep well under the logic node to shield it.
8. A computer program for predicting a logic soft error rate of a circuit of a given technology, wherein the computer program has as inputs a database of logic soft error rate data points and the circuit, the computer program comprising:
code for calculating a charge stored on at least one logic node in the circuit;
code for estimating a logic soft error rate of a logic node in the circuit using the database of data points, the area of the logic node, the charge stored on the logic node, and the technology of the circuit.
code for calculating the logic soft error rate for the circuit as a function of the logic soft error rate for the at least one logic node.
9. The computer program of claim 8, wherein the data points used by the code for estimating a logic soft error rate is further a function of a product of the circuit.
10. The computer program of claim 8, wherein the code for calculating the logic soft error rate for the circuit calculates the logic soft error rate for the circuit by summing the logic soft error rates for each logic node in the circuit.
11. The computer program of claim 8, further comprising code for ranking each logic node according to the logic soft error rate of each node.
12. The computer program of claim 8, further comprising code for determining a subset of logic nodes.
13. The computer program of claim 12, wherein the code for determining the subset of logic nodes determines the subset of logic nodes based, at least on part, on a target logic soft error rate of the circuit.
14. The computer program of claim 13, wherein the target soft error rate is determined by a user of the program.
15. The computer program of claim 13, further comprising code for suggesting actions to take to reduce the logic soft error rate for each logic node in the subset of logic nodes.
16. The computer program of claim 15, wherein the suggested actions include at least one of the following for each logic node in the subset of logic nodes:
decreasing the area of the logic node;
adding additional capacitance to the logic node; and
placing a deep well under the logic node to shield it.
17. The computer program of claim 12, wherein the subset of logic nodes consists of logic nodes with a logic soft error rate above a certain value.
18. The computer program of claim 17, wherein the certain value is set by a user of the computer program.
19. The computer program of claim 8, wherein the computer program is run on a general application computer.
20. The computer program of claim 19, wherein the computer program accesses the database using a network.