1. A method of manufacturing a thin film transistor substrate, comprising:
sequentially forming a semiconductor layer, a first insulation layer and a second insulation layer, on a base substrate;
forming a first photoresist pattern on the second insulation layer and having a first thickness portion, and a second thickness portion thinner than the first thickness portion;
removing exposed portions of the second insulation layer, the first insulation layer and the semiconductor layer using the first photoresist pattern as a mask, to form an intermediate insulation pattern, a first insulation pattern and a semiconductor pattern from the second insulation layer, the first insulation layer and the semiconductor layer, respectively;
reducing an entirety of the first photoresist pattern by a thickness of the second thickness portion, to form a second photoresist pattern having a third thickness and expose a portion of the intermediate insulation pattern;
removing the exposed portion of the intermediate insulation pattern using the second photoresist pattern as a mask, to form a second insulation pattern from the intermediate insulation pattern; and
forming a gate electrode on and overlapping both the first insulation pattern and the second insulation pattern.
2. The method of claim 1, wherein the first insulation pattern comprises a material having a dielectric constant greater than about 10.
3. The method of claim 1, further comprising:
forming an inorganic insulation layer on the base substrate comprising the gate electrode thereon;
forming a first contact hole penetrating the inorganic insulation layer, the second insulation pattern and the first insulation pattern, to partially expose a first end portion of the semiconductor pattern, and forming a second contact hole penetrating the inorganic insulation layer and the first insulation pattern, to partially expose a second end portion of the semiconductor pattern; and
forming a drain electrode electrically connected to the first end portion of the semiconductor pattern through the first contact hole, and forming a source electrode electrically connected to the second end portion of the semiconductor pattern through the second contact hole.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor integrated circuit, comprising:
a reconfigurable circuit including a plurality of computing units interconnected in a reconfigurable manner;
a processing circuit including at least one of a fixed logic circuit configured to perform predetermined processing and a parameter-defined special-purpose hardware unit configured to change processing specifications according to parameter settings;
a network having reconfigurable connections and coupled to said reconfigurable circuit and to said processing circuit; and
at least two interfaces each coupled to said network to provide external coupling for said network.
2. The semiconductor integrated circuit as claimed in claim 1, further comprising, in addition to a set of said reconfigurable circuit, said processing circuit, and said network, one or more sets of another reconfigurable circuit, another processing circuit, and another network, wherein said network of said set and the networks of said one or more sets are connected in series through said interfaces, and the networks situated at opposite ends of said series are connectable to an exterior of said semiconductor integrated circuit through said interfaces.
3. The semiconductor integrated circuit as claimed in claim 1, wherein said network includes:
a plurality of signal lines; and
a selector configured to select a predetermined number of signal lines from said plurality of signal lines,
wherein only the predetermined number of signal lines selected by said selector are coupled to one of said interfaces.
4. The semiconductor integrated circuit as claimed in claim 1, further comprising:
a bus coupled to said reconfigurable circuit and said processing circuit; and
a processor coupled to said bus.
5. The semiconductor integrated circuit as claimed in claim 4, further comprising a control circuit configured to control the connections of said network, wherein said control circuit is configured to set the connections of said network in response to instruction supplied from said processor.
6. The semiconductor integrated circuit as claimed in claim 4, wherein said reconfigurable circuit is configured to define what computations are performed by said plurality of computing units in response to setting data supplied from said processor.
7. The semiconductor integrated circuit as claimed in claim 4, further comprising a system interface configured to couple said processor to an external system.
8. The semiconductor integrated circuit as claimed in claim 1, wherein said network includes a crossbar configured to interconnect between said reconfigurable circuit and said processing circuit.
9. The semiconductor integrated circuit as claimed in claim 1, wherein said parameter-defined special-purpose hardware unit includes:
a special-purpose hardware configured to perform predetermined processing; and
a setting register configured to store therein data that defines operation and processing specifications of said special-purpose hardware.
10. The semiconductor integrated circuit as claimed in claim 1, wherein said processing circuit further includes an interface configured to exchange a signal with an exterior of said semiconductor integrated circuit.