1. A holey fiber comprising:
a core region at a center of the holey fiber;
a cladding region around the core region;
a plurality of holes included in the cladding region, formed in layers around the core region, arranged to form a triangular lattice having a lattice constant \u039b of 2.5 micrometers to 4.5 micrometers, and each having a diameter of d micrometers; and
a wavelength dispersion value of \u221210 psnmkm to 10 psnmkm at a wavelength of 1050 nanometers when d\u039b is 0.4 to 0.47, wherein
a number of the layers of the plurality of holes is equal to or less than seven,
a confinement loss of the holey fiber at the wavelength of 1050 nanometers is equal to or less than 0.1 dBkm,
an effective core area of the holey fiber at the wavelength of 1050 nanometers is equal to or larger than 10 \u03bcm2, and
the holey fiber demonstrates a single-mode operation at a wavelength of 1000 nanometers.
2. The holey fiber according to claim 1, wherein a confinement loss of a lowest order mode among higher-order optical propagation modes of the holey fiber at the wavelength of 1050 nanometers is equal to or more than 100 dBm.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of effecting hardware acceleration of broadcast operations in a parallel computer, the parallel computer comprising a plurality of compute nodes organized for collective operations via a data communications network, each compute node having a receive buffer, the method comprising:
establishing a network topology for the data communications network;
selecting, in dependence upon the network topology, a schedule for a broadcast operation;
depositing, by a root node of the topology, broadcast data in a target node’s receive buffer, including performing a DMA operation with a well-known memory location for the target node’s receive buffer;
depositing, by the root node in a memory region designated for storing broadcast data length for the target node, a length of the broadcast data, including performing a DMA operation with a well-known memory location of the broadcast data length memory region; and
2. The method of claim 1 wherein depositing broadcast data further comprises:
packetizing the broadcast data into one or more broadcast data packets; and enabling, in a header of the broadcast data packets, a deposit flag, the enabled deposit flag representing an instruction to any compute node receiving the broadcast data packet to store a copy of the broadcast data packet.
3. The method of claim 1 wherein depositing a length of the broadcast data further comprises:
packetizing the length of the broadcast data into one or more broadcast data length packets; and
enabling, in a header of the broadcast data length packets, a deposit flag, the enabled deposit flag representing an instruction to any compute node receiving the broadcast data length packet to store a copy of the broadcast data length packet.
4. (canceled)
5. The method of claim 1 wherein establishing within the network a topology further comprises:
defining the compute nodes in the network topology; and
initializing, by each compute node, a DMA data descriptor, the DMA data descriptor comprising:
the compute node’s receive buffer;
the compute node’s broadcast data length memory region; and
a well-known memory location of another compute node’s receive buffer.
6. The method of claim 5 further comprising depositing, by the target node, the broadcast data in the subsequent target node’s receive buffer including performing a DMA operation with the well-known memory location of the subsequent target node’s receive buffer included in the target node’s DMA data descriptor and in accordance with the broadcast data length size stored in the target node’s broadcast data length memory region.
7. An apparatus for effecting hardware acceleration of broadcast operations in a parallel computer, the parallel computer comprising a plurality of compute nodes organized for collective operations via a data communications network, each compute node having a receive buffer, the apparatus comprising a computer processor and a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions capable of:
establishing a network topology for the data communications network;
selecting, in dependence upon the network topology, a schedule for a broadcast operation;
depositing, by a root node of the topology, broadcast data in a target node’s receive buffer, including performing a DMA operation with a well-known memory location for the target node’s receive buffer;
depositing, by the root node in a memory region designated for storing broadcast data length for the target node, a length of the broadcast data, including performing a DMA operation with a well-known memory location of the broadcast data length memory region; and
8. The apparatus of claim 7 wherein depositing broadcast data further comprises:
packetizing the broadcast data into one or more broadcast data packets; and
enabling, in a header of the broadcast data packets, a deposit flag, the enabled deposit flag representing an instruction to any compute node receiving the broadcast data packet to store a copy of the broadcast data packet.
9. The apparatus of claim 7 wherein depositing a length of the broadcast data further comprises:
packetizing the length of the broadcast data into one or more broadcast data length packets; and
enabling, in a header of the broadcast data length packets, a deposit flag, the enabled deposit flag representing an instruction to any compute node receiving the broadcast data length packet to store a copy of the broadcast data length packet.
10. (canceled)
11. The apparatus of claim 7 wherein establishing within the network a topology further comprises:
defining the compute nodes in the network topology; and
initializing, by each compute node, a DMA data descriptor, the DMA data descriptor comprising:
the compute node’s receive buffer;
the compute node’s broadcast data length memory region; and
a well-known memory location of another compute node’s receive buffer.
12. The apparatus of claim 11 further comprising computer program instructions capable of depositing, by the target node, the broadcast data in the subsequent target node’s receive buffer including performing a DMA operation with the well-known memory location of the subsequent target node’s receive buffer included in the target node’s DMA data descriptor and in accordance with the broadcast data length size stored in the target node’s broadcast data length memory region.
13. A computer program product for effecting hardware acceleration of broadcast operations in a parallel computer, the parallel computer comprising a plurality of compute nodes organized for collective operations via a data communications network, each compute node having a receive buffer, the computer program product disposed in a computer readable storage medium, the computer program product comprising computer program instructions capable of:
establishing a network topology for the data communications network;
selecting, in dependence upon the network topology, a schedule for a broadcast operation;
depositing, by a root node of the topology, broadcast data in a target node’s receive buffer, including performing a DMA operation with a well-known memory location for the target node’s receive buffer;
depositing, by the root node in a memory region designated for storing broadcast data length for the target node, a length of the broadcast data, including performing a DMA operation with a well-known memory location of the broadcast data length memory region; and
14. The computer program product of claim 13 wherein depositing broadcast data further comprises:
packetizing the broadcast data into one or more broadcast data packets; and enabling, in a header of the broadcast data packets, a deposit flag, the enabled deposit flag representing an instruction to any compute node receiving the broadcast data packet to store a copy of the broadcast data packet.
15. The computer program product of claim 13 wherein depositing a length of the broadcast data further comprises:
packetizing the length of the broadcast data into one or more broadcast data length packets; and
enabling, in a header of the broadcast data length packets, a deposit flag, the enabled deposit flag representing an instruction to any compute node receiving the broadcast data length packet to store a copy of the broadcast data length packet.
16. (canceled)
17. The computer program product of claim 13 wherein establishing within the network a topology further comprises:
defining the compute nodes in the network topology; and
initializing, by each compute node, a DMA data descriptor, the DMA data descriptor comprising:
the compute node’s receive buffer;
the compute node’s broadcast data length memory region; and
a well-known memory location of another compute node’s receive buffer.
18. The computer program product of claim 17 further comprising computer program instructions capable of depositing, by the target node, the broadcast data in the subsequent target node’s receive buffer including performing a DMA operation with the well-known memory location of the subsequent target node’s receive buffer included in the target node’s DMA data descriptor and in accordance with the broadcast data length size stored in the target node’s broadcast data length memory region.
19. The computer program product of claim 13, wherein the computer readable storage medium comprises a transmission medium.
20. The computer program product of claim 13, wherein the computer readable storage medium comprises a recordable medium.