1. A method for forming a FinFET, comprising:
forming a relaxed silicon germanium (Si1-XGeX) body region for a fully depleted Fin field effect transistor (FinFET) having a body thickness of at least 10 nanometers (nm) for a process design rule of less than 25 nm;
forming a source and a drain on opposing ends of the body region, wherein the source and the drain are formed with halo ion implantation; and
forming a gate opposing the body region and separated therefrom by a gate dielectric,
wherein the method includes epitaxially growing a germanium (Ge) layer on a sidewall on the body region to provide biaxial compressive strain to the body region in forming a PMOS FinFET.
2. The method of claim 1, wherein the method includes epitaxially growing the Ge layer on the sidewall on the body region to a thickness of approximately 12 nm.
3. The method of claim 1, wherein the method includes forming a channel between the source and the drain having a width less than 35 nm and a length less than 25 nanometers.
4. The method of claim 1, wherein forming the source and the drain with halo ion implantation includes:
forming a p-type source and drain having a Boron (B) dopant at a concentration of 2\xd71020 atomscm3; and
forming a halo ion implant underneath the p-type source drain having a concentration of 2\xd71018 atomscm3.
5. The method of claim 1, wherein forming the source and the drain with halo ion implantation includes:
forming an n-type source and drain having an Arsenic (As) dopant at a concentration of 2\xd71020 atomscm3; and
forming a halo ion implant underneath the n-type source and drain having a concentration of 2\xd71018 atomscm3.
6. A method for forming a FinFET, comprising:
forming a relaxed silicon germanium (Si1-XGeX) body region for a fully depleted Fin field effect transistor (FinFET) having a body thickness of at least 10 nanometers (nm) for a process design rule of less than 25 nm;
forming a substitute gate over the body region;
forming a source and a drain on opposing ends of the body region, wherein the source and the drain are formed with halo ion implantation;
annealing the source and the drain before removing the substitute gate; and
forming a gate separated from the body region by a gate dielectric.
7. The method of claim 6, wherein the method includes forming a source extension and a drain extension while the substitute gate is present on the device.
8. The method of claim 6, wherein the method includes epitaxially growing a germanium (Ge) sidewall on the body region to provide biaxial compressive strain on the body region in forming a PMOS FinFET.
9. The method of claim 6, wherein the method includes epitaxially growing a silicon (Si) sidewall on the body region to provide biaxial tensile strain on the body region in forming an NMOS FinFET.
10. The method of claim 6, wherein forming the relaxed silicon germanium (Si1-XGeX) body region includes forming a forming a relaxed silicon germanium (Si1-XGeX) where X is in a range of 0.5 to 0.6.
11. The method of claim 6, wherein annealing the source and the drain before removing the substitute gate includes annealing at a temperature in a range of 850 degrees Celsius to 1050 degrees Celsius for a period of at least 5 seconds to activate the source and the drain.
12. The method of claim 11, wherein forming the gate includes forming a metal gate separated from the body region by a dielectric material having a dielectric constant (K) greater than 12.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A multi-protocol serial interface system comprising:
a multi-protocol port pin array comprising a plurality of port pins, wherein the plurality of port pins compatibly interface with a plurality of external systems, each port pin using a different serial communication method;
a transport protocol change Field Protocol Gate Array (FPGA), wherein a plurality of different transport protocols are preconfigured with a protocol gate array logic circuit, and when one transport protocol is selected, the transport protocol change FPGA is connected with the port pins of the multi-protocol port pin array depending on the selected protocol; and
a pull-up change FPGA for regulating a pull-up load of the port pins connected with the transport protocol change FPGA.
2. The multi-protocol serial interface system according to claim 1, wherein roles of the port pins of the multi-protocol port pin array are changed depending on the protocol selected in the transport protocol change FPGA.
3. The multi-protocol serial interface system according to claim 1, wherein the transport protocol change FPGA selects a protocol depending on code data stored in a plurality of coding cells.
4. The multi-protocol serial interface system according to claim 3, wherein the coding cell comprises a register for storing data with a nonvolatile capacitor.
5. The multi-protocol serial interface system according to claim 1, wherein the transport protocol change FPGA is connected with a port pin interfacing with the external system among the port pins of the multi-protocol port pin array in response to code data stored in the plurality of coding cells.
6. The multi-protocol serial interface system according to claim 5, wherein the coding cell comprises a register for storing data with a nonvolatile capacitor.
7. The multi-protocol serial interface system according to claim 1, wherein the transport protocol change FPGA is programmed so that inputoutput terminals for a power voltage and a ground voltage are fixed as a specific terminal regardless of a kind of selected protocol.
8. The multi-protocol serial interface system according to claim 1, wherein the pull-up change FPGA comprises a plurality of coding cells for storing pull-up load regulating data to regulate pull-up load of the port pins connected with the transport protocol change FPGA; and
a load unit for regulating pull-up load of the corresponding port pins in response to the pull-up load regulating data.
9. The multi-protocol serial interface system according to claim 8, wherein the coding cell comprises a register for storing data with a nonvolatile capacitor.
10. The multi-protocol serial interface system according to claim 8, wherein the load unit is a MOS transistor for applying a power voltage to the corresponding port pin in response to the pull-up load regulating data.
11. A multi-protocol serial interface system comprising:
a multi-protocol port pin array comprising a plurality of port pins, wherein the plurality of port pins compatibly interface with a plurality of external systems, each port pin using a different serial communication method;
a plurality of protocol change FPGAs, wherein each of the protocol change FPGAs is preconfigured with a different protocol gate array logic circuit, and one of the protocol change FPGAs is selected to process data received through the port pins of the multi-protocol port pin array;
a plurality of registers for selectively connecting the port pins interfacing with the external system among the port pins of the multi-protocol port pin array with the selected protocol change FPGA; and
a pull-up change FPGA for regulating pull-up load of the port pins connected with the transport protocol change FPGA.
12. The multi-protocol serial interface system according to claim 11, wherein roles of the port pins of the multi-protocol port pin array are changed depending on the selected protocol change FPGA.
13. The multi-protocol serial interface system according to claim 11, wherein the protocol change FPGA is selected depending on code data stored in a plurality of coding cells.
14. The multi-protocol serial interface system according to claim 13, wherein the coding cell comprises a register for storing data with a nonvolatile capacitor.
15. The multi-protocol serial interface system according to claim 11, wherein the protocol change FPGA is programmed so that inputoutput terminals for a power voltage and a ground voltage are fixed as a specific terminal.
16. The multi-protocol serial interface system according to claim 11, wherein the pull-up change FPGA comprises a plurality of coding cells for storing pull-up load regulating data to regulate pull-up load of the port pins connected with the selected protocol change FPGA; and
a load unit for regulating pull-up load of the corresponding port pins in response to the pull-up load regulating data.
17. The multi-protocol serial interface system according to claim 16, wherein the coding cell comprises a register for storing data with a nonvolatile capacitor.
18. The multi-protocol serial interface system according to claim 16, wherein the load unit is a MOS transistor for applying a power voltage to the corresponding port pin in response to the pull-up load regulating data.