1. A method for forming a multi-level integrated circuit semiconductor device with improved resistance to delamination comprising the steps of:
providing a semiconductor wafer comprising a metallization layer comprising wiring interconnect structures with an uppermost etch stop layer;
forming at least one adhesion promoting layer on the etch stop layer, wherein the adhesion promoting layer comprises an atomic substituent common to both the IMD layer and the etch stop layer, said adhesion promoting layer having an improved adhesion strength to an overlying inter-metal dielectric (IMD) layer compared to an adhesion strength between said etch stop layer and said IMD layer;
forming said inter-metal dielectric (IMD) layer on the at least one adhesion promoting layer; and,
forming damascene wiring interconnect structures in the IMD layer.
2. The method of claim 1, wherein the atomic substituent comprises an atomic concentration gradient increasing in a direction toward the IMD layer.
3. The method of claim 1, wherein the adhesion promoting layer comprises multiple layers each layer sequentially increasing in atomic concentration of the atomic substituents in a direction toward the IMD layer.
4. The method of claim 1, wherein the atomic substituent is selected from the group consisting of silicon, nitrogen, and oxygen.
5. The method of claim 1, wherein the adhesion promoting layer comprises the same atomic substituents as the etch stop layer in addition to an increased atomic oxygen concentration.
6. The method of claim 1, wherein the adhesion promoting layer is selected from the group consisting of silicon oxynitride, oxygen doped silicon carbide, and nitrogen doped silicon carbide.
7. The method of claim 1, wherein the etch stop layer is selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbide, oxygen doped silicon carbide, and nitrogen doped silicon carbide.
8. The method of claim 1, wherein the etch stop layer and the adhesion promoting layer are formed in-situ by a PECVD process.
9. The method of claim 1, wherein the adhesion promoting layer and the IMD layer are formed in-situ by a PECVD process.
10. The method of claim 1, wherein the IMD layer comprises silicon oxide.
11. The method of claim 1, wherein the IMD layer is selected from the group consisting of carbon doped oxide and organo-silicate glass (OSG).
12. The method of claim 1, wherein the adhesion promoting layer is formed by an oxidizing plasma process on the first etch stop layer.
13. The method of claim 1, wherein the adhesion promoting layer is formed by a wet chemical oxidizing process on the first etch stop layer.
14. The method of claim 1, wherein the adhesion promoting layer comprises a dielectric layer formed of the same material as the IMD layer and having a dielectric constant higher than the IMD layer.
15. The method of claim 1, further comprising forming a stress adjustable passivation layer over an uppermost metallization layer comprising bonding pads.
16. The method of claim 15, wherein the stress adjustable passivation layer is formed with a stress level comprising a stress type of one of tensile and compressive to counteract a stress type and level present in underlying metallization layers.
17. The method of claim 15, further comprising the step of forming a stress transition layer between the uppermost metallization layer and the stress adjustable passivation layer, said stress transition layer comprising a stress level intermediate between the stress type and level present in underlying metallization layers and the stress adjustable passivation layer.
18. The method of claim 17, wherein the stress adjustable passivation layer and the stress transition layer are selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbide, oxygen doped silicon carbide, and nitrogen doped silicon carbide.
19. The method of claim 15, further comprising the steps of:
forming a chip;
forming a first layer of molding material adjacent the chip having a first coefficient of thermal expansion (CTE); and,
forming a second layer of molding material on the first layer of molding material having a second CTE larger than the first CTE.
20. The method of claim 19, wherein the first layer comprises a filler material having a higher thermal conductivity compared to filler material for the second layer.
21. The method of claim 19, wherein the first layer comprises a material having a higher volume of porosity with respect to an arbitrary volume of the material compared to the second layer.
22. A method for forming a multi-level integrated circuit semiconductor device with improved resistance to delamination comprising the steps of:
providing a semiconductor wafer comprising a metallization layer comprising wiring interconnect structures with an uppermost etch stop layer;
forming at least one adhesion promoting layer on the etch stop layer, wherein the adhesion promoting layer comprises an atomic substituent common to both the IMD layer and the etch stop layer, said adhesion promoting layer having an improved adhesion strength to an overlying inter-metal dielectric (IMD) layer compared to an adhesion strength between said etch stop layer and said IMD layer;
forming said IMD layer on the at least one adhesion promoting layer, said IMD layer comprising damascene wiring interconnect structures therein; and,
forming a stress adjustable passivation layer over an uppermost metallization layer comprising bonding pads, said stress adjustable passivation layer formed with a stress level comprising a stress type of one, of tensile and compressive to counteract a stress type and level present in underlying metallization layers.
23. A method for forming a multi-level integrated circuit semiconductor device with improved resistance to delamination comprising the steps of:
providing a semiconductor wafer comprising a metallization layer comprising wiring interconnect structures with an uppermost etch stop layer;
forming at least one adhesion promoting layer on the etch stop layer, wherein the adhesion promoting layer comprises an atomic substituent common to both the IMD layer and the etch stop layer, said adhesion promoting layer having an improved adhesion strength to an overlying inter-metal dielectric (IMD) layer compared to an adhesion strength between said etch stop layer and said IMD layer;
forming said IMD layer on the at least one adhesion promoting layer, said IMD layer comprising damascene wiring interconnect structures therein;
forming a stress adjustable passivation layer over an uppermost metallization layer comprising bonding pads, said stress adjustable passivation layer formed with a stress level comprising a stress type of one of tensile and compressive to counteract a stress type and level present in underlying metallization layers;
forming a chip;
forming a first layer of molding material adjacent the chip having a first coefficient of thermal expansion (CTE); and,
forming a second layer of molding material on the first layer of molding material having a second CTE larger than the first CTE.
24. The method of claim 23, wherein the adhesion promoting layer is selected from the group consisting of silicon, nitrogen, an oxygen.
25. The method of claim 24, wherein the atomic substituent comprises an atomic concentration gradient increasing in a direction toward the IMD layer.
26. The method of claim 23, wherein the adhesion promoting layer is selected from the group consisting of silicon oxynitride, oxygen doped silicon carbide, and nitrogen doped silicon carbide.
27. The method of claim 23, wherein the etch stop layer is selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbide, oxygen doped silicon carbide, and nitrogen doped silicon carbide.
28. The method of claim 23, wherein the etch stop layer and the adhesion promoting layer are formed by a PECVD process.
29. The method of claim 23, where the IMD layer comprises silicon oxide.
30. The method of claim 23, wherein the adhesion promoting layer comprises a dielectric layer formed of the same material as the IMD layer having a dielectric constant higher than the IMD layer.
31. The method of claim 23, further comprising the step of forming a stress transition layer between the uppermost metallization layer and the stress adjustable passivation layer, said stress transition layer comprising a stress level intermediate between the stress type and level present in underlying metallization layers and the stress adjustable passivation layer.
32. The method of claim 23, wherein the stress adjustable passivation layer and the stress transition layer are selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbide, oxygen doped silicon carbide, and nitrogen doped silicon carbide.
33. The method of claim 23, wherein the first layer comprises a filler material having a higher thermal conductivity compared to filler material for the second layer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A power drive unit for supplying current to an electric motor, comprising;
a heat sink;
a power module pressed by a press member to the heat sink to be fastened thereto; and
a spring member that has a substantially circular shape and is installed between the power module and the press member.
2. The power drive unit according to claim 1, further including:
a projection that protrudes from the press member to be engaged with an engagement hole bored at the center of the spring member.
3. A power drive unit for supplying current to an electric motor, comprising;
a heat sink;
a plurality of power modules pressed by a press member to the heat sink to be fastened thereto; and
a spring member that has a substantially circular shape and is installed between each of the power modules and the press member.
4. The power drive unit according to claim 3, wherein the press member is bored with a screw inserting hole and the heat sink is bored with a screw hole at a position corresponding to the screw inserting hole.
5. The power drive unit according to claim 4, wherein a plurality of the power modules are placed at a same distance from the screw inserting hole.
6. The power drive unit according to claim 1, further including:
a case that accommodates the press member; and
a rotation preventer provided on the case to prevent the press member from rotating.
7. The power drive unit according to claim 3, wherein a plurality of the power modules are arranged in zigzag on the heat sink.
8. The power drive unit according to claim 7, further including:
a capacitor that is connected to each of the power modules and is installed in a space defined by the adjacent power modules on the heat sink.
9. The power drive unit according to claim 3, wherein a number of a plurality of the power modules is two.
10. The power drive unit according to claim 3, wherein a number of a plurality of the power modules is three.
11. The power drive unit according to claim 3, wherein a number of a plurality of the power modules is six.