1. A method of forming an electric wiring, the method comprising:
forming a main trench and first and second guide trenches on a substrate, the first and second guide trenches being disposed at opposite sides of the main trench;
ejecting ink into the main trench, the ink including a conductive material; and
heating the substrate to,
sinter the ink such that the electric wiring is formed an upper portion of the main trench, and
contract the ink such that a tunnel is formed in a lower portion of the main trench.
2. The method of claim 1, wherein the ejecting the ink includes ejecting ink so as to contact an upper surface of a first trench wall between the main trench and the first guide trench and an upper surface of a second wall between the main trench and the second guide trench.
3. The method of claim 2, wherein the forming the main trench and the forming the first and second guide trenches includes forming each trench such that a sum of a width of an upper surface of the first trench wall and a width of an upper surface of the second trench wall is greater than a width of a bottom surface of the main trench.
4. The method of claim 2, wherein the ejecting the ink includes ejecting a solvent of the ink at a contact angle of greater than about 30 degrees with respect to the surface of the substrate.
5. The method of claim 2, wherein the ink has a sintering temperature ranging from about 100\xb0 C. to about 500\xb0 C.
6. The method of claim 1, further comprising:
performing an ink-phobic surface treatment with respect to a surface of the substrate after forming the main trench and the first and second guide trenches.
7. The method of claim 6, wherein the performing the ink-phobic surface treatment includes coating fluorine on the surface of the substrate.
8. The method of claim 1, further comprising:
planarizing an upper surface of the electric wiring after the forming of the electric wiring.
9. The method of claim 1, wherein the forming the main trench and the forming the first and second guide trenches includes patterning the substrate via dry etching using a photolithography method.
10. The method of claim 1, wherein the ejecting the ink is for an inkjet printing method.
11. The method of claim 1, wherein the ink comprises one of a polar and a non-polar solvent.
12. The method of claim 1, wherein the conductive material comprises metal nanoparticles.
13. The method of claim 1, wherein the substrate comprises at least one of glass and silicon.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A camera comprising a main body and a display device attached to the main body, said display device comprising:
at least one first thin film transistor formed over a substrate and electrically connected to a pixel electrode, said first thin film transistor comprising:
a semiconductor layer having a pair of impurity regions and a channel region extending therebetween;
a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, and
a pair of LDD regions between the channel region and the pair of impurity regions,
a driver circuit formed over the substrate for driving said at least one first thin film transistor, said driver circuit including at least a second n-channel TFT and a third n-channel TFT,
wherein said second n-channel TFT comprises:
a semiconductor layer having source and drain regions and a channel region therebetween, and an LDD region interposed between the channel region and the drain region while the source region is contiguous to the channel region; and
a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, wherein the gate electrode overlaps an entire portion of the LDD region, and
wherein said third n-channel TFT comprises:
a semiconductor layer having a pair of impurity regions and a channel region therebetween, and a pair of LDD regions interposed between the channel region and the pair of impurity regions; and
a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, wherein the gate electrode partly overlaps the pair of LDD regions.
2. The camera according to claim 1 wherein said camera is a video camera.
3. The camera according to claim 1 wherein said camera is a digital camera.
4. The camera according to claim 1 wherein said first thin film transistor comprises an offset region.
5. A camera comprising a main body and a display device attached to the main body, said display device comprising:
at least one first thin film transistor formed over a substrate and electrically connected to a pixel electrode, said first thin film transistor comprising:
a semiconductor layer having a pair of impurity regions and a channel region extending therebetween;
a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, and
a pair of LDD regions between the channel region and the pair of impurity regions,
an interlayer insulating film comprising an organic resin formed over the first thin film transistor;
a storage capacitor electrically connected to the pixel electrode, said storage capacitor comprising:
a shielding film formed over the interlayer insulating film;
a portion of the pixel electrode overlapping the shielding film with a dielectric film interposed therebetween wherein the dielectric film comprises an oxide of a material of the shielding film,
a driver circuit formed over the substrate for driving said at least one first thin film transistor, said driver circuit including at least a second n-channel TFT and a third n-channel TFT,
wherein said second n-channel TFT comprises:
a semiconductor layer having source and drain regions and a channel region. therebetween, and an LDD region interposed between the channel region and the drain region while the source region is contiguous to the channel region; and
a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, wherein the gate electrode overlaps an entire portion of the LDD region, and
wherein said third n-channel TFT comprises:
a semiconductor layer having a pair of impurity regions and a channel region therebetween, and a pair of LDD regions interposed between the channel region and the pair of impurity regions; and
a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, wherein the gate electrode partly overlaps the pair of LDD regions.
6. The camera according to claim 5 wherein said camera is a video camera.
7. The camera according to claim 5 wherein said camera is a digital camera.
8. The camera according to claim 5 wherein said first thin film transistor comprises an offset region.
9. A camera comprising a main body and a display device attached to the main body, said display device comprising:
at least one first thin film transistor formed over a substrate and electrically connected to a pixel electrode, said first thin film transistor comprising:
a semiconductor layer having a pair of impurity regions and a channel region extending therebetween;
a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, and
a pair of LDD regions between the channel region and the pair of impurity regions,
a driver circuit formed over the substrate for driving said at least one first thin film transistor, said driver circuit including at least a second n-channel TFT and a third n-channel TFT,
wherein said second n-channel TFT comprises:
a semiconductor layer having source and drain regions and a channel region therebetween, and an LDD region interposed between the channel region and the drain region while the source region is contiguous to the channel region; and
a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, wherein the gate electrode overlaps an entire portion of the LDD region, and
wherein said third n-channel TFT comprises:
a semiconductor layer having a pair of impurity regions and a channel region therebetween, and a pair of LDD regions interposed between the channel region and the pair of impurity regions; and
a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, wherein the gate electrode partly overlaps the pair of LDD regions,
wherein said third n-channel TFT is a part of a sampling circuit of the driver circuit.
10. The camera according to claim 9 wherein said camera is a video camera.
11. The camera according to claim 9 wherein said camera is a digital camera.
12. The camera according to claim 9 wherein said first thin film transistor comprises an offset region.
13. A camera comprising a main body and a display device attached to the main body, said display device comprising:
at least one first thin film transistor formed over a substrate and electrically connected to a pixel electrode, said first thin film transistor comprising:
a semiconductor layer having a pair of impurity regions and a channel region extending therebetween;
a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, and
a pair of LDD regions between the channel region and the pair of impurity regions,
a driver circuit formed over the substrate for driving said at least one first thin film transistor, said driver circuit including at least a second n-channel TFT and a third n-channel TFT,
wherein said second n-channel TFT comprises:
a semiconductor layer having source and drain regions and a channel region therebetween, and an LDD region interposed between the channel region and the drain region while the source region is contiguous to the channel region; and
a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, wherein the gate electrode overlaps an entire portion of the LDD region, and
wherein said third n-channel TFT comprises:
a semiconductor layer having a pair of impurity regions and a channel region therebetween, and a pair of LDD regions interposed between the channel region and the pair of impurity regions; and
a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, wherein the gate electrode partly overlaps the pair of LDD regions,
wherein said second n-channel TFT is a part of at least one of a shift register, a frequency dividing circuit, a signal splitting circuit, a level shifter or a buffer circuit of the driver circuit.
14. The camera according to claim 13 wherein said camera is a video camera.
15. The camera according to claim 13 wherein said camera is a digital camera.
16. The camera according to claim 13 wherein said first thin film transistor comprises an offset region.
17. A computer comprising a main body and a display device attached to the main body, said display device comprising:
at least one first thin film transistor formed over a substrate and electrically connected to a pixel electrode, said first thin film transistor comprising:
a semiconductor layer having a pair of impurity regions and a channel region extending therebetween;
a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, and
a pair of LDD regions between the channel region and the pair of impurity regions,
a driver circuit formed over the substrate for driving said at least one first thin film transistor, said driver circuit including at least a second n-channel TFT and a third n-channel TFT,
wherein said second n-channel TFT comprises:
a semiconductor layer having source and drain regions and a channel region therebetween, and an LDD region interposed between the channel region and the drain region while the source region is contiguous to the channel region; and
a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, wherein the gate electrode overlaps an entire portion of the LDD region, and
wherein said third n-channel TFT comprises:
a semiconductor layer having a pair of impurity regions and a channel region therebetween, and a pair of LDD regions interposed between the channel region and the pair of impurity regions; and
a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, wherein the gate electrode partly overlaps the pair of LDD regions.
18. The computer according to claim 17 further comprising a keyboard.
19. The computer according to claim 17 further comprising an image receiving section.
20. The computer according to claim 17 wherein said first thin film transistor comprises an offset region.
21. A computer comprising a main body and a display device attached to the main body, said display device comprising:
at least one first thin film transistor formed over a substrate and electrically connected to a pixel electrode, said first thin film transistor comprising:
a semiconductor layer having a pair of impurity regions and a channel region extending therebetween;
a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, and
a pair of LDD regions between the channel region and the pair of impurity regions,
an interlayer insulating film comprising an organic resin formed over the first thin film transistor;
a storage capacitor electrically connected to the pixel electrode, said storage capacitor comprising:
a shielding film formed over the interlayer insulating film;
a portion of the pixel electrode overlapping the shielding film with a dielectric film interposed therebetween wherein the dielectric film comprises an oxide of a material of the shielding film,
a driver circuit formed over the substrate for driving said at least one first thin film transistor, said driver circuit including at least a second n-channel TFT and a third n-channel TFT,
wherein said second n-channel TFT comprises:
a semiconductor layer having source and drain regions and a channel region therebetween, and an LDD region interposed between the channel region and the drain region while the source region is contiguous to the channel region; and
a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, wherein the gate electrode overlaps an entire portion of the LDD region, and
wherein said third n-channel TFT comprises:
a semiconductor layer having a pair of impurity regions and a channel region therebetween, and a pair of LDD regions interposed between the channel region and the pair of impurity regions; and
a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, wherein the gate electrode partly overlaps the pair of LDD regions.
22. The computer according to claim 21 further comprising a keyboard.
23. The computer according to claim 21 further comprising an image receiving section.
24. The computer according to claim 21 wherein said first thin film transistor comprises an offset region.
25. A computer comprising a main body and a display device attached to the main body, said display device comprising:
at least one first thin film transistor formed over a substrate and electrically connected to a pixel electrode, said first thin film transistor comprising:
a semiconductor layer having a pair of impurity regions and a channel region extending therebetween;
a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, and
a pair of LDD regions between the channel region and the pair of impurity regions,
a driver circuit formed over the substrate for driving said at least one first thin film transistor, said driver circuit including at least a second n-channel TFT and a third n-channel TFT,
wherein said second n-channel TFT comprises:
a semiconductor layer having source and drain regions and a channel region therebetween, and an LDD region interposed between the channel region and the drain region while the source region is contiguous to the channel region; and
a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, wherein the gate electrode overlaps an entire portion of the LDD region, and
wherein said third n-channel TFT comprises:
a semiconductor layer having a pair of impurity regions and a channel region therebetween, and a pair of LDD regions interposed between the channel region and the pair of impurity regions; and
a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, wherein the gate electrode partly overlaps the pair of LDD regions,
wherein said third n-channel TFT is a part of a sampling circuit of the driver circuit.
26. The computer according to claim 25 further comprising a keyboard.
27. The computer according to claim 25 further comprising an image receiving section.
28. The computer according to claim 25 wherein said first thin film transistor comprises an offset region.
29. A computer comprising a main body and a display device attached to the main body, said display device comprising:
at least one first thin film transistor formed over a substrate and electrically connected to a pixel electrode, said first thin film transistor comprising:
a semiconductor layer having a pair of impurity regions and a channel region extending therebetween;
a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, and
a pair of LDD regions between the channel region and the pair of impurity regions,
a driver circuit formed over the substrate for driving said at least one first thin film transistor, said driver circuit including at least a second n-channel TFT and a third n-channel TFT,
wherein said second n-channel TFT comprises:
a semiconductor layer having source and drain regions and a channel region therebetween, and an LDD region interposed between the channel region and the drain region while the source region is contiguous to the channel region; and
a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, wherein the gate electrode overlaps an entire portion of the LDD region, and
wherein said third n-channel TFT comprises:
a semiconductor layer having a pair of impurity regions and a channel region therebetween, and a pair of LDD regions interposed between the channel region and the pair of impurity regions; and
a gate electrode adjacent to the channel region with a gate insulating film interposed therebetween, wherein the gate electrode partly overlaps the pair of LDD regions,
wherein said second n-channel TFT is a part of at least one of a shift register, a frequency dividing circuit, a signal splitting circuit, a level shifter or a buffer circuit of the driver circuit.
30. The computer according to claim 29 wherein said camera is a video camera.
31. The computer according to claim 29 wherein said camera is a digital camera.
32. The computer according to claim 29 wherein said first thin film transistor comprises an offset region.