1. A memory device, comprising:
a memory cell array having at least a first memory cell group, a second memory cell group and a redundancy memory cell group, the first memory cell group including a plurality of first memory cells associated with a first data line, the second memory cell group including a plurality of second memory cells associated with a second data line, and the redundancy memory cell group including a plurality of redundancy memory cells associated with a redundancy data line;
a data line selection circuit configured to provide a data path between an inputoutput node and one of the first data line, the second data and the redundancy data line.
2. The memory device of claim 1, further comprising:
selection control logic configured to control the data line selection circuit based on a selected output data width for the memory device.
3. The memory device of claim 1, wherein the selection control logic is configured to control the data line selection circuit based on the selected output data width for the memory device and whether a defective memory cell in one of the first and second memory cell groups is detected.
4. The memory device of claim 1, further comprising:
selection control logic configured to control the data line selection circuit based on whether a defective memory cell in one of the first and second memory cell groups is detected.
5. The memory device of claim 1, wherein the data line selection circuit includes a multiplexer configured to provide the data path between the inputoutput node and one of the first data line, the second data line and the redundancy data line.
6. The memory device of claim 1, wherein
the memory cell array includes first to nth memory cell groups, where n is greater than or equal to 2, each of the first to nth memory cell groups is associated with first to nth data lines, respectively; and
the data line selection circuit is configured to provide data paths between (i) the redundancy data line and the first to nth data lines and (ii) first to nth inputoutput nodes.
7. The memory device of claim 6, wherein
the data line selection circuit includes first to nth selection units, each of the first to nth selection units is configured to selectively provide a data path between a connection node and one of a set of selection nodes, the connection node of each of the first to nth selection units being associated with a respective one of the first to nth inputoutput nodes;
the first selection unit having at least one selection node connected to the redundancy data line and having at least another selection node connected to the first data line;
the second selection unit having one selection node connected to the redundancy data line, having at least another selection node connected to the first data line and having yet another selection node connected to the second data line; and
the ith selection unit having three selection nodes respectively connected to the (i\u22122)th data line, the (i\u22121th) data line and the ith data line where i is 3 to n.
8. The memory device of claim 7, further comprising:
selection control logic configured to control the data line selection circuit based on the selected output data width for the memory device and whether a defective memory cell in one of the first to nth memory cell groups is detected.
9. The memory device of claim 8, wherein the selection control logic is configured to control the data line selection circuit to provide a data path between the ith memory cell group and the ith inputoutput node if the selected output data width is eight, wherein i is between 1 and 8.
10. The memory device of claim 9, wherein the selection control logic is configured to replace access via one of the first to eighth data lines with access via the redundancy data line if a detected defective memory cell exists in the one of the first to eight memory cell groups.
11. The memory device of claim 10, wherein if the kth memory cell group includes the detected defective memory cell, then the selection control logic is configured to control the data line selection circuit such that the first though kth inputoutput nodes are connected to the redundancy data line and the first through (k\u22121)th data lines, and the (k+1)th to the eighth inputoutput nodes are connected the (k+1)th to eighth data lines.
12. The memory device of claim 10, wherein if the kth memory cell group includes the detected defective memory cell, then the selection control logic is configured to control the data line selection circuit such that the first though (k\u22121)th inputoutput nodes are connected to the first through (k\u22121)th inputoutput nodes, and the kth to the eighth inputoutput nodes are connected the (k+1)th to eighth data lines and the redundancy data line.
13. The memory device of claim 9, wherein the selection control logic controls the data lines selection circuit to provide a data path between the mth data line and the mth inputoutput node if the selected output data width is four, wherein in is 1, 3, 5 and 7 in the odd operation mode and m is 2, 4, 6 and 8 in the even operation mode.
14. The memory device of claim 13, wherein the selection control logic is configured to replace access via one of the first, third, fifth and seventh data lines with access via the redundancy data line if a detected defective memory cell exists in the one of the first, third, fifth and seventh memory cell groups in the odd operation mode, and the selection control logic is configured to replace access via one of the second, fourth, sixth and eighth data lines with access via the redundancy data line if a detected defective memory cell exists in the one of the second, fourth, sixth and eighth memory cell groups in the even operation mode.
15. The memory device of claim 8, wherein the selection control logic is configured to control the data line selection circuit to provide a data path between the ith memory cell group and the ith inputoutput node if the selected output data width is one of 16, 32 and 64, wherein i is between 1 and one of 16, 32 and 64.
16. The memory device of claim 15, wherein the selection control logic is configured to replace access via one of the first to pth data lines with access via the redundancy data line if a detected defective memory cell exists in the one of the first to pth memory cell groups, where p is one of 16, 32 and 64.
17. The memory device of claim 8, wherein
the memory cell array includes first and second redundancy memory cell groups, the first redundancy memory cell group including a plurality of first redundancy memory cells associated with a first redundancy data line, and the second redundancy memory cell group including a plurality of second redundancy memory cells associated with a second redundancy data line; and
the data line selection circuit is configured to provide data paths between (i) the first and second redundancy data lines and the first to nth data lines and (ii) the first to nth inputoutput nodes.
18. The memory device of claim 7 wherein each of the first to nth selection units includes a 3:1 multiplexer.
19. The memory device of claim 7, wherein at least one of the first to nth data lines is connected to a sense amplifier arranged in a lengthwise direction of the memory cell array, and the redundancy data line is connected to a sense amplifier arranged in a widthwise direction of the memory cell array.
20. The memory device of claim 1, wherein at least one of the first and second data lines is connected to a sense amplifier arranged in a lengthwise direction of the memory cell array, and the redundancy data lines is connected to a sense amplifier arranged in a widthwise direction of the memory cell array.
21. A memory device, comprising:
a memory cell array having at least first through nth memory cell groups and first and second redundancy memory cell groups, where n is greater than or equal to four, the first through nth memory cell groups associated with respective first through nth data lines, the first redundancy memory cell group associated with a first redundancy data line and the second redundancy memory cell group associated with a second redundancy data line; and
a data line selection circuit configured to replace access to one of the first through nth memory cell groups via a respective one of the first through nth data lines with access to the first redundancy memory cell group via the first redundancy data line, and configured to simultaneously replace access to another of the first through nth memory cell groups via a respective one of the first through nth data lines with access to the second redundancy memory cell group via the second redundancy data line.
22. The memory device of claim 21, further comprising:
selection control logic configured to control the data line selection circuit based on the selected output data width for the memory device and whether a defective memory cell in one of the first to nth memory cell groups is detected.
23. The memory device of claim 22, wherein the selection control logic is configured to control the data line selection circuit to provide a data path between the ith memory cell group and the ith inputoutput node if the selected output data width is eight, wherein i is between 1 and 8, and n is at least 8.
24. The memory device of claim 23, wherein the selection control logic is configured to replace access via one of the first to mth data lines with access via the first redundancy data line if a detected defective memory cell exists in the one of the first to mth memory cell groups, and the selection control logic is configured to replace access via one of the (m+1)th to nth data lines via the second redundancy data if a detected defective memory cell exists in one of the (m+1)th to nth memory cell groups.
25. The memory device of claim 23 wherein the selection control logic controls the data lines selection circuit to provide a data path between the mth data line and the mth inputoutput node if the selected output data width is four, wherein m is 1, 3, 5 and 7 in the odd operation mode and m is 2, 4, 6 and 8 in the even operation mode.
26. The memory device of claim 25, wherein the selection control logic is configured to simultaneously replace access via two of the first, third, fifth and seventh data lines with access via the first and second redundancy data lines if a detected defective memory cell exists in the two of the first, third, fifth and seventh memory cell groups in the odd operation mode, and the selection control logic is configured to replace access via two of the second, fourth, sixth and eighth data lines with access via the first and second redundancy data lines if a detected defective memory cell exist in the two of the second, fourth, sixth and eighth memory cell groups in the even operation mode.
27. The memory device of claim 22, wherein the selection control logic is configured to control the data line selection circuit to provide a data path between the ith memory cell group and the ith inputoutput node if the selected output data width is one of 16, 32 and 64, wherein i is between 1 and one of 16, 32 and 64, and n is at least one of 32 and 64.
28. The memory device of claim 27, wherein the selection control logic is configured to replace access via two of the first to pth data lines with access via the first and second redundancy data line if a detected defective memory cell exists in the one of the first to pth data lines, where p is one of 16, 32 and 64.
29. The memory device of claim 21, wherein the data line selection circuit include first to nth selection units, each of the first to nth selection units associated with one of the first to nth inputoutput nodes, and each of the first to nth selection units includes a 3:1 multiplexer.
30. The memory device of claim 21, wherein at least one of the first to nth data lines is connected to a sense amplifier arranged in a lengthwise direction of the memory cell array, and at least one of the first to nth data lines is connected to a sense amplifier arranged in a widthwise direction of the memory cell array.
31. A memory device, comprising:
a memory array having a plurality of memory cell groups and a redundancy memory cell group, each memory cell group associated with a respective data line, the redundancy memory cell group associated with a redundancy data line;
a plurality of inputoutput nodes;
a data line selection circuit configured to provide data paths between (i) the plurality of inputoutput nodes and (ii) the data lines and the redundancy data line, the data line selection circuit including a selection unit associated with each of the plurality of inputoutput nodes, each selection unit associated with only two of the redundancy data line and the data lines, and the data line selection circuit configured to provide data paths between odd ones of the plurality of inputoutput nodes and odd ones of the data lines in an odd mode of operation, and configured to provide data paths between even ones of the plurality of inputoutput nodes and even ones of the data lines in an even mode of operation, and the data line selection circuit configured to replace access via one of the data lines with access via the redundancy data line such that a detected defective memory cell in one of the plurality of memory cell groups is replaced with one of the plurality of redundancy memory cells regardless of the even and odd operating mode.
32. The memory device of claim 31, wherein the plurality of memory cell groups includes first to nth memory cell groups associated with first to nth data lines;
the plurality of inputoutput nodes includes first to nth inputoutput nodes;
the plurality of selection units includes first to nth selection units, each of the first to nth selection units configured to provide a data path between a connection node and one of two selection nodes, the connection node of each of the first to nth selection units associated with a respective one of the first to nth inputoutput nodes;
the first selection unit having one of the two selection nodes associated with the redundancy data line and another of the two selection nodes associated with the first data line;
the second selection unit having one of the two selection nodes associated with the redundancy data line and another of the two selection nodes associated with the second data line; and
the ith selection unit having one of the two selection nodes associated with the (i\u22122)th data line and another of the two selection nodes associated with the ith data line.
33. The memory device of claim 32, wherein each of the first to nth selection units is a 2:1 multiplexer.
34. The memory device of claim 32, further comprising:
an evenodd selection unit connected to the redundancy data line and configured to provide a data path between the redundancy data line and one of an even redundancy data line and an odd redundancy data line based on the even and odd operating mode;
the first selection unit having one of the two selection nodes associated with the odd redundancy data line; and
the second selection unit having one of the two selection nodes associated with the even redundancy data line.
35. The memory device of claim 34, wherein the evenodd selection unit includes a demultiplexer.
36. The memory device of claim 34, wherein the evenodd selection unit includes a first switch selectively connecting the redundancy data line and the odd redundancy data line, and the evenodd selection unit includes a second switch selectively connecting the redundancy data line and the even redundancy data line.
37. The memory device of claim 34 further comprising:
selection control logic configured to control the data line selection circuit and the evenodd selection unit based on whether the even or odd operation mode has been selected.
38. The memory device of claim 37, wherein the selection control logic is configured to control the data line selection circuit based on whether the even or odd operation mode has been selected and whether a defective memory cell in one of the first to nth memory cell groups is detected.
39. The memory device of claim 38, wherein the selection control logic includes a storage device storing a mode indicator indicating whether the even or odd operation mode has been selected.
40. The memory device of claim 32, further comprising:
selection control logic configured to control the data line selection circuit based on a selected output data width for the memory device and whether a defective memory cell in one of the first to nth memory cell groups is detected.
41. The memory device of claim 32, wherein
the selection control logic controls the data lines selection circuit to provide a data path between the mth data line and the mth inputoutput node if the selected output data width is eight, and m is 1 to 8;
the selection control logic controls the data lines selection circuit to provide a data path between the kth data line and the kth inputoutput node if the selected output data width is four, wherein k is 1, 3, 5 and 7 in the odd operation mode and k is 2, 4, 6 and 8 in the even operation mode.
42. A memory device, comprising:
a first memory cell array including a first plurality of memory cell groups and a first redundancy memory cell group, each of the first plurality of memory cell groups associated with respective first data lines, the first redundancy memory cell group associated with one of the first data lines;
a second memory cell array including a second plurality of memory cell groups and a second redundancy memory cell group, each of the second plurality of memory cell group associated with respective second data lines, and the second redundancy memory cell group associated with one of the second data lines;
a data line selection circuit configured to selectively provide data paths between the first data lines and a first set of a plurality of inputoutput nodes, and configured to selectively provide data paths between the second data lines and a second set of the plurality of inputoutput nodes, the data line selection circuit configured to selectively replace a detected defective memory cell in the first plurality of memory groups with a redundancy memory cell in the second redundancy memory cell group.
43. The memory device of claim 42, wherein further comprising:
a first column decoder associated with the first memory cell array;
a second column decoder associated with the second memory cell array;
a row decoder associated with both the first and second memory cell array.
44. The memory device of claim 42, wherein the data line selection circuit includes a plurality of selection units, each selection unit associated with one of the plurality of inputoutput nodes, and at least one of the selection units associated with an inputoutput node of the first set connected to at least one of the first data lines and connected to the second data line associated with the second redundancy memory cell group.
45. The memory device of claim 44, wherein at least one of the selection units associated with an inputoutput node of the second set is connected to at least one of the second data lines and connected to the first data line associated with the first redundancy memory cell group.
46. The memory device of claim 42, wherein the data line selection circuit is configured to selectively replace a detected defective memory cell in the second plurality of memory groups with a redundancy memory cell in the first redundancy memory cell group.
47. The memory device of claim 42, wherein the first and second memory cell arrays are on different chips.
48. The memory device of claim 42, wherein the first set of the plurality of inputoutput nodes and the second set of the plurality of inputoutput nodes share same inputoutput nodes.
49. A method of replacing defective memory cells in a memory cell array having at least a first memory cell group, a second memory cell group and a redundancy memory cell group, the first memory cell group including a plurality of first memory cells associated with a first data line, the second memory cell group including a plurality of second memory cells associated with a second data line, and the redundancy memory cell group including a plurality of redundancy memory cells associated with a redundancy data line, the method comprising:
providing a data path between an inputoutput node and one of the first data line, the second data and the redundancy data line.
50. A method of replacing defective memory cells in a memory cell array having at least first through nth memory cell groups and first and second redundancy memory cell groups, where n is greater than or equal to four, the first through nth memory cell groups associated with respective first through nth data lines, the first redundancy memory cell group associated with a first redundancy data line and the second redundancy memory cell group associated with a second redundancy data line, the method comprising:
replacing access to one of the first through nth memory cell groups via a respective one of the first through nth data lines with access to the first redundancy memory cell group via the first redundancy data line; and
simultaneously replacing access to another of the first through nth memory cell groups via a respective one of the first through nth data lines with access to the second redundancy memory cell group via the second redundancy data line.
51. A method of replacing defective memory cells in a memory array having a plurality of memory cell groups and a redundancy memory cell group, each memory cell group associated with a respective data line, the redundancy memory cell group associated with a redundancy data line, the method comprising:
providing data paths between (i) a plurality of inputoutput nodes and (ii) the data lines and the redundancy data line using a plurality of selection units, each selection unit associated with one of the plurality of inputoutput nodes, each selection unit associated with only two of the redundancy data line and the data lines, the providing including, providing data paths between odd ones of the plurality of inputoutput nodes and odd ones of the data lines in an odd mode of operation,
providing data paths between even ones of the plurality of inputoutput nodes and even ones of the data lines in an even mode of operation, and
replacing access via one of the data lines with access via the redundancy data line such that a detected defective memory cell in one of the plurality of memory cell groups is replaced with one of the plurality of redundancy memory cells regardless of the even and odd operating mode.
52. A method of replacing defective memory cells in a memory device include a first memory cell array and a second memory cell array, the first memory cell array including a first plurality of memory cell groups and a first redundancy memory cell group, each of the first plurality of memory cell groups associated with respective first data lines, the first redundancy memory cell group associated with one of the first data lines, the second memory cell array including a second plurality of memory cell groups and a second redundancy memory cell group, each of the second plurality of memory cell groups associated with respective second data lines, and the second redundancy memory cell group associated with one of the second data lines, the method comprising:
selectively replacing a detected defective memory cell in the first plurality of memory groups with a redundancy memory cell in the second redundancy memory cell group.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A forwarding method of an Ethernet Passive Optical Network (EPON) bridge apparatus, which executes bridging between a network port and a PON port including a plurality of logical ports via Logical Link Identifier (LLID) assigned to an Optical Network Unit (ONU) in the PON, the method comprising steps of:
receiving frame from the network port or the PON port;
associating the port through which the frame was received with the source MAC address of the received frame and recording that information to the FDB table adapted to keep the port information for the MAC addresses;
searching the FDB table for the destination MAC address of the received frame to get the port information of destination MAC address;
(i) forwarding the received frame to the network port after removing LLID therefrom, if the upstream frame’s destination MAC address is looked up to be present in the network port; and
(ii) forwarding the received frame to the PON port after adding the LLID corresponding to destination MAC address to the received frame, if the destination MAC address is looked up to be present in the lower PON port.
2. The forwarding method according to claim 1, further comprising steps of:
having a VID-LLID table for each VID value of the input frames so that the input VID value can be used as the entry address of the VID-LLID table, and each entry containing the LLID value to attach for the corresponding VID in the downstream process and information on whether the VLAN tag addition for the upstream frame and VLAN tag removal for the downstream frame is to be done in the ONU side and not in the OLT;
having an LLID-VID table for each LLID value of the upstream frame so that the input LLID value can be used as the entry address of the LLID-VID table, and each entry containing VLAN tag information to add for the corresponding LLID.
3. The forwarding method according to claim 1, further comprising recording LLID value to be replaced with for each registered multicast group MAC address, for a plurality of arbitrary multicast addresses in a multicast table.
4. The forwarding method according to claim 3, wherein the multicast table’s each entry includes 23 lower bits of registered multicast MAC address and LLID value corresponding to the registered multicast address.
5. The forwarding method according to claim 1, wherein the FDB table has its entry address obtained by hash calculation on MAC address of the input frame, the entry including MAC address, port information for the MAC address, and corresponding LLID information in case where MAC address is present in the PON port.
6. The forwarding method according to claim 1, wherein the forwarding step (ii) comprises:
if the received frame is upstream frame inputted from the PON port, replacing LLID of the received frame with LLID corresponding to destination MAC address to transfer it to the PON port.
7. The forwarding method according to claim 6, wherein the forwarding step (ii) comprises:
if LLID of the received frame is identical to LLID corresponding to destination MAC address, discarding the received frame.
8. The forwarding method according to claim 1, further comprising:
in case where LLID corresponding to destination MAC address of the received frame is unknown, if the received frame is downstream data inputted from the network port, adding broadcast LLID to the received frame to transmit it to the PON port, and
removing LLID from the received frame to transfer it to the network port, if the received frame is upstream data inputted from the PON port, and at the same time replacing the LLID of the received frame with the its anti-LLID to forward it to the PON port.
9. The forwarding method according to claim 2, wherein the forwarding step (i) further comprises:
if the received frame is upstream frame inputted from the PON port, referring to the LLID-VID conversion table and attaching VLAN tag corresponding to the input LLID attached to the received frame to forward it to the network port.
10. The forwarding method according to claim 2, wherein the forwarding step (ii) further comprises:
searching the VID-LLID conversion table with the VID included in VLAN tag and attaching LLID corresponding to the VID to the received frame to forward the received frame to the PON port, if the received frame is inputted from the network port and includes VLAN tag.
11. The forwarding method according to claim 9 or 10, wherein with respect to the VID-LLID conversion table, VLAN tag in the received frame is maintained for the VID registered to have VLAN tag insertionremoval in the ONU side.
12. The forwarding method according to claim 9, wherein in case of attaching VLAN tag, LLID included in the received frame is removed.
13. The forwarding method according to claim 10, wherein in case of attaching LLID, VLAN tag included in the received frame is removed.
14. The forwarding method according to claim 3, wherein the forwarding step (ii) comprises:
if the received frame is multicast frame inputted from the network port, referring to the multicast table and replacing the LLID of the received frame with the LLID corresponding to the multicast address to forward it to the PON port.
15. An Ethernet Passive Optical Network (EPON) bridge apparatus for executing bridging between a network port and a PON port including a plurality of logical ports via Logical Link Identifier (LLID) assigned to an Optical Network Unit (ONU) of the PON, comprising:
an FDB table adapted to keep MAC address and its associated port information for the learned MAC addresses, and if the port is the PON side, the LLID value as the port information;
a downstream input buffer adapted to store downstream frames inputted from the network port until they are bridged;
a downstream lookup and learner adapted to read downstream frame stored in the downstream input buffer, learn the port information for the source MAC address of the downstream frame and record the learned information in the FDB table, attach destination LLID corresponding to destination MAC address of the downstream frame to the frame by referring to the FDB table;
a downstream output buffer adapted to store downstream frames inputted from the downstream lookup and learner until they are transmitted to the PON port;
an upstream input buffer adapted to store upstream frames inputted from the PON port until they are bridged;
an upstream lookup and learner adapted to read upstream frames stored in the upstream input buffer, record the learned information in the FDB table by associating source MAC address of the upstream frame to the source LLID of the upstream frame from the PON port, refer to the FDB table to get the port information on destination MAC address of the upstream frame, and if the port is in the network side, output the upstream frame to the upstream output buffer after removing the source LLID of the upstream frame; and
an upstream output buffer adapted to store upstream frames outputted from the upstream lookup and learner until they are outputted to the network port.
16. The EOPN bridge apparatus according to claim 15, further comprising:
a reflection output buffer adapted to store upstream frame outputted from the upstream lookup and learner and output the stored frame to the PON port when selected,
wherein the upstream lookup and learner is further adapted to, if destination MAC address of the upstream frame is present in the PON port, attach LLID of destination MAC address obtained by referring to the FDB table to the upstream frame to output it to the reflection output buffer.
17. The EPON bridge apparatus according to claim 16, wherein if destination MAC address of the inputted upstream frame is present in the PON port, and searched destination LLID and source LLID on the upstream frame are identical, the upstream lookup and learner is adapted to discard the upstream frame.
18. The EPON bridge apparatus according to claim 16, wherein the upstream lookup and learner is adapted to, if destination MAC address of the inputted upstream frame is not registered in the FDB table, attach anti-LLID corresponding to existing LLID to the upstream frame to output the same to the reflection output buffer and at the same time forward the upstream frame to the upstream VLAN tag processor without removing LLID.
19. The EPON bridge apparatus according to claim 16, further comprising:
a VID-LLID conversion table adapted to keep the LLID value to be attached to downstream frame according to VID value of the input frame; and
a LLID-VID conversion table adapted to keep the VLAN tag value to add to the upstream frame according to the input LLID value.
20. The EPON bridge apparatus according to claim 19, further comprising a downstream VLAN tag processor adapted to use VID value contained in the downstream frame inputted from the downstream lookup and learner, search the VID-LLID conversion table to correct LLID of the downstream frame into LLID corresponding to the VID and remove the VLAN tag.
21. The EPON bridge apparatus according to claim 19, further comprising an upstream VLAN tag processor adapted to search VLAN tag information corresponding to the LLID value of the upstream frame inputted from the upstream lookup and learner in the LLID-VID conversion table, and add the VLAN tag having VID corresponding to the LLID of the upstream frame to output it to the upstream output buffer,
wherein in a VLAN operation mode, the upstream lookup and learner is adapted to output the upstream frame with LLID still attached to the upstream VLAN tag inserter.
22. The EPON bridge apparatus according to claim 21, wherein the VID-LLID conversion table further comprises information indicating whether or not the VLAN tag addition in the upstream and VLAN tag removal in the downstream is to be done in the ONU side.
23. The EPON bridge apparatus according to claim 22, wherein the upstreamdownstream VLAN tag processor is adapted to, if the VID associated with the upstreamdownstream frame is set up to maintain VLAN tag, forward the downstream frame without removing VLAN tag and forward the upstream frame without adding VLAN tag.
24. The EPON bridge apparatus according to claim 15, further comprising a multicast table adapted to manage multicast address having group membership in the PON port for downstream frame and LLID corresponding thereto.
25. The EPON bridge apparatus according to claim 24, further comprising a downstream multicast processor adapted to check whether or not the downstream frame transferred from the lookup and learner or the downstream VLAN tag processor has multicast address as destination MAC address, and in the case of multicast address, search LLID information pertaining to the MAC address in the multicast table, and then replace LLID of the downstream frame with the searched LLID to forward it to the downstream output buffer.
26. The EPON bridge apparatus according to claim 24, further comprising a reflection multicast processor adapted to, if destination MAC address of frame outputted to the PON side provided with new destination LLID by the upstream lookup and learner of the upstream frame is multicast address, check whether or not the multicast address is registered in the multicast table, and if registered, convert LLID value of the frame into searched LLID value in the multicast table to output the frame to the reflection output buffer.
27. The EPON bridge apparatus according to claim 26, further comprising a frame extraction queue adapted to store frame to be processed by CPU, inform the CPU of every frame stored through interrupt, provide the number and lengths of the stored frames to the CPU enabling the CPU to read the flames;
a frame insertion queue adapted to store frame outputted from CPU, and if frame is stored inside, issue a read request; and
a processor interface adapted to interface to ensure the external CPU to insert or extract frame intofrom the frame extraction queue or the frame insertion queue,
wherein the downstream lookup and learner is adapted to extract frame destined to the CPU out of the downstream frames read from the downstream input buffer to forward the frame to the frame extraction queue.
28. The EPON bridge apparatus according to claim 27, further comprising:
an upstream intermediate buffer adapted to store frames outputted from the upstream lookup and learner or upstream VLAN tag processor until they are transmitted to the network port, and output a read request along with information on frame length if there is at least one frame inside; and
an upstream multiplexer adapted to selectively read frames from the frame insertion queue or upstream intermediate buffer at the request of the frame insertion queue or upstream intermediate buffer to transfer them to the upstream output buffer.
29. An Ethernet Passive Optical Network (EPON) bridge apparatus for executing bridging between a network port and a PON port including a plurality of logical ports via Logical Link Identifier (LLID) assigned to each Optical Network Unit (ONU), comprising:
an FDB table adapted to keep MAC address and its associated port information for the learned MAC addresses, and LLID value corresponding to MAC address if the port is in the PON side;
a VID-LLID conversion table adapted to keep the LLID value to be attached to downstream frame according to the input VID value;
a LLID-VID conversion table adapted to keep the VLAN tag value to be added according to the input LLID for upstream frame;
a multicast table adapted to store registered multicast addresses for downstream frame with LLID value corresponding thereto;
a downstream input buffer adapted to store downstream frames inputted from the network port they are being bridged;
a downstream input buffer adapted to read downstream frame stored in the downstream input buffer, record port information on source MAC address of the downstream frame in the FDB table, refer to destination MAC address andor VLAN tag of the downstream frame, look up the FDB table, VID-LLID conversion table and multicast table, selectively remove VLAN tag, confirm destination LLID and then attach VLAN tag to the downstream frame to output;
a downstream input buffer adapted to store downstream frames inputted from the downstream frame processor until they are transmitted to the PON port;
an upstream input buffer adapted to store upstream frames inputted from the PON port until they are bridged;
an upstream frame processor adapted to read upstream frame stored in the upstream input buffer, associate source MAC address, source LLID of the upstream frame and PON port to record the information in the FDB table, refer to the FDB table, LLID-VID conversion table and multicast table to send the frame to the destination port including PON port after looking for the destination port or LLID value associated with the destination MAC address of the upstream frame, remove LLID of the upstream frame and selectively attach VLAN tag corresponding to the removed LLID to output the frame to the upstream output buffer; and
an upstream output buffer adapted to store upstream frames inputted from the upstream lookup and learner until they are outputted to the network port.
30. The EPON bridge apparatus according to claim 29, further comprising a reflection output buffer adapted to store upstream frame outputted from the upstream frame processor and then output the stored frame to the PON port when downstream transmission is selected,
wherein the upstream frame processor is adapted to, if destination MAC address of the upstream frame is present in the PON port, attach to the upstream frame destination LLID obtained by referring to the FDB table or multicast table, and output the upstream frame to the reflection output buffer.
31. The EPON bridge apparatus according to claim 30, wherein the upstream frame processor is adapted to, if destination MAC address of the inputted upstream frame is present in the PON port, and searched destination LLID and source LLID in the upstream frame are identical, discard the corresponding upstream frame.
32. The EPON bridge apparatus according to claim 30, wherein the upstream frame processor is adapted to, if destination MAC address of the inputted upstream frame is not registered on the FDB table, attach anti-LLID corresponding to existing LLID to the upstream frame to output it to the reflection output buffer while sending the frame to the upstream output buffer after removing the LLID.
33. The EPON bridge apparatus according to claim 30, wherein the VID-LLID conversion table further comprises information indicating whether or not the VLAN tag addition in the upstream and VLAN tag removal in the downstream is to be done in the ONU side for each registered VID,
wherein the upstreamdownstream frame processor is adapted to, if the VLAN tag is set up to be maintained for the VID, forward the downstream frame without removing VLAN tag and forward the upstream frame without adding VLAN tag.
34. The EPON bridge apparatus according to claim 30, further comprising:
a frame extraction queue adapted to store frame to be processed by CPU out of downstream frames, inform the CPU of every frame stored through interrupt, provide the number and lengths of the stored frames to the CPU enabling the CPU to read the frames;
a frame insertion queue adapted to store frame outputted from CPU, and if frame is stored inside, issue a read request; and
a processor interface adapted to interface to enable the external CPU to insert or extract frame intofrom the frame extraction queue or frame insertion queue,
wherein the downstream lookup and learner is adapted to extract frame destined to the CPU out of downstream frames read by the downstream input buffer and send the same to the frame extraction queue.
35. The EPON bridge apparatus according to claim 34, further comprising:
an upstream intermediate buffer adapted to store frames outputted from the upstream lookup and learner or the upstream VLAN tag processor until they are transmitted to the network port, and if there is at least one frame inside, output a read request along with information on frame lengths; and
an upstream multiplexer adapted to selectively read frame from the frame insertion queue or upstream intermediate buffer at the request of the frame insertion queue or upstream intermediate buffer to transfer the frame to the upstream output buffer.