1. A microbial mixture composition characterized by having DNA signature bands at about 3189 base pairs and at about 1737 base pairs.
2. The composition of claim 1, further comprising having DNA signature bands at about 3437 base pairs, at about 991 base pairs and at about 676 base pairs.
3. The composition of claim 1, further comprising the mixture characterized by having about 23% relative ratio of me equal to 264 and about 38% relative ratio of me equal to 414.
4. The microbial mixture composition of claim 1, comprising a prokaryote, a yeast or mixtures thereof.
5. A bioremediation system produced by a process comprising the steps of preparing a predetermined volume of a media having (i) less than about 2 ppm chlorine, (ii) a pH in the range of about 6.0 to about 9.0, (iii) a nutrient source having about 30% nitrogen, about 10% phosphate, and about 10% potassium, (iv) an enzyme and (v) a yeast cell; adding a starter bacteria, wherein the starter bacteria comprises at least one cell of an anaerobic bacteria and at least one cell of an aerobic bacteria; and incubating for at least about 36 hours at a temperature in the range of about 20\xb0 C. to about 37\xb0 C. to provide a liquid bioremediation system.
6. The product according to claim 5, wherein Bacillus sp. is the anaerobic bacteria, the aerobic bacteria, or both the anaerobic and the aerobic bacteria.
7. The product of claim 5, wherein the enzyme digests a carbohydrate, a protein, a lipid, or a surfactant.
8. The product of claim 5, wherein the yeast is a Saccharomyces sp.
9. The product of claim 5, further comprising adding elements selected from the group consisting of iron, boron, manganese, zinc, molybdenum, copper, or combinations thereof.
10. The product of claim 5, further comprising maintaining the predetermined volume by adding water having less than 2 ppm chlorine.
11. The product of claim 5, further comprising maintaining the phosphorous, nitrogen and potassium compositions.
12. The product of claim 5, further comprising the step of adding to the liquid bioremediation system a starch selected from the group consisting of corn meal, wheat bran, rice bran, or other cellulosic material to form a solid.
13. A method of operating a sewage treatment system comprising treating sewage with a microbial composition according to claim 1 for a time sufficient to reduce an amount of solid matter in the sewage without removing mass from the sewage treatment system.
14. The method of claim 13, wherein the solid matter is reduced by about 100% relative to the initial amount of solid matter.
15. The method of claim 13, wherein the solid matter comprises total suspended solids or volatile suspended solids.
16. The method of claim 15, wherein the total suspended solids is reduced by about 36% in about five days.
17. The method of claim 15, wherein the total suspended solids is reduced by an amount in the range of about 34% to about 40% over a period of time up to about 18 days.
18. The method of claim 15, wherein the volatile suspended solids are reduced by about 30% in about five days.
19. The method of claim 15, wherein the volatile suspended solids are reduced by an amount in the range of about 23% to about 36% in about 18 days.
20. The method of claim 13, wherein the sewage comprises dissolved oxygen in an amount of at least about 0.5 ppm.
21. The method of claim 13, wherein the sewage comprises dissolved oxygen in an amount of at least about 1.0 ppm.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for manufacturing a semiconductor device, comprising:
forming a T-shape dummy gate structure on the substrate;
removing the T-shape dummy gate structure to form a T-shape gate trench; and
forming a T-shape metal gate structure by filling a metal layer in the T-shape gate trench.
2. The method according to claim 1, wherein the step of forming the T-shape dummy gate structure further comprises:
forming a dummy gate stack structure consisting of a gate insulation layer and a dummy gate layer on the substrate;
forming a gate spacer on both sides of the dummy gate stack structure with the height of the gate spacer less than the height of the dummy gate stack structure to expose the top of the dummy gate stack structure; and
forming a dummy gate epitaxial layer on both the exposed top and side of the dummy gate stack structure, wherein the dummy gate epitaxial layer and the dummy gate layer together constitute the T-shape dummy gate structure.
3. The method according to claim 2, wherein an SD epitaxial layer is formed on both sides of gate spacer at the same time when the dummy gate epitaxial layer is formed.
4. The method according to claim 3, wherein an SD heavily doped region is formed by doping the SD epitaxial layer at the same time when or after the SD epitaxial layer is formed.
5. The method according to claim 2, wherein the step of forming the gate spacer further comprises: forming a spacer material layer on the substrate and on the dummy gate layer; over etching the spacer material layer so that the height of the formed gate spacer is less than the height of the dummy gate stack structure.
6. The method according to claim 2, wherein an SD extension region andor a halo-SD region is formed on the substrate on both sides of the dummy gate stack structure after the dummy gate stack structure is formed and before the gate spacer is formed.
7. The method according to claim 1, wherein an interlayer dielectric layer is formed on the substrate and is planarized until the T-shape dummy gate structure is exposed after the T-shape dummy gate structure is formed and before the T-shape dummy gate structure is removed.
8. The method according to claim 1, wherein the metal layer comprises a work function adjusting layer and a metal gate filling layer.
9. The method according to claim 8, wherein the work function adjusting layer comprises TiN, TaN, and combinations thereof, and the metal gate filling layer comprises Ti, Ta, W, Al, Cu, Mo, and combinations thereof.
10. The method according to claim 2, wherein the gate insulation layer comprises high k materials.
11. The method according to claim 2, wherein the dummy gate layer comprises polycrystalline silicon, amorphous silicon, microcrystalline silicon, amorphous carbon, hydrogenated amorphous carbon, and combinations thereof.
12. The method according to claim 2, wherein the gate spacer comprises silicon nitride, silicon oxynitride, DLC, and combinations thereof.
13. The method according to claim 2, wherein the width difference between the top and bottom of the T-shape dummy gate structure is no greater than the width of the gate spacer.
14. A semiconductor device, comprising: a substrate, a gate insulation layer with high k materials on the substrate, a T-shape metal gate structure on the gate insulation layer, and an SD region on both sides of the T-shape metal gate structure.