What is claimed is:
1. A device for performing working operations on a workpiece, said device comprising:
a table;
a shaft fixedly secured to said table, said shaft having an axis;
a support housing supporting a motor and a working tool driven by said motor, said support housing being disposed on said shaft adjacent to said table, said support housing being axially movable along said shaft and being laterally pivotable about an axis of rotation; and
a locking mechanism for locking the support housing at a predetermined lateral position, wherein said locking mechanism comprises a handle disposed on said shaft, said handle being rotatable in two directions with respect to said shaft, such that rotation of said handle on said shaft urges said support housing into contact with said table.
2. The device according to claim 1, wherein said locking mechanism further comprises a cam disposed on said shaft between said handle and said support housing.
3. The device according to claim 1, wherein the shaft axis is substantially parallel to the axis of rotation.
4. The device according to claim 1, wherein the shaft axis corresponds to the axis of rotation.
5. The device according to claim 1, wherein the shaft has a first surface having a first thread disposed thereon in a first orientation, and a second surface having a second thread disposed thereon in a second orientation, said first and second thread intersect forming a V-shaped thread.
6. The device according to claim 1, wherein said device is a compound miter saw.
7. An apparatus for moving a member axially along a shaft, said apparatus comprising:
a first shaft surface having a first thread disposed thereon in a first orientation;
a second shaft surface having a second thread disposed thereon in a second orientation, wherein said first and second thread intersect forming a V-shaped thread portion;
a handle disposed on said shaft, said handle having a thread engaging portion contacting said V-shaped thread portion and being rotatable in two directions with respect to said shaft, such that rotation of said handle on said shaft causes said axial movement along said shaft of both said handle and said member.
8. A method for operating a device comprising a table, a shaft fixedly secured to said table, said shaft having an axis, a support housing supporting a motor and a working tool driven by said motor, said support housing being disposed on said shaft adjacent to said table, said support housing being axially movable along said shaft and being laterally pivotable about an axis of rotation, and a locking mechanism for locking the support housing at a predetermined lateral position, wherein said locking mechanism comprises a handle disposed on said shaft, said handle being rotatable in two directions with respect to said shaft, said method comprising the steps of:
adjusting lateral position of said support housing; and
rotating said handle in one of said two directions;
wherein rotation of said handle on said shaft urges said support housing into contact with said table.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A clocked inverter comprising:
first to third transistors electrically connected in series, and
a fourth transistor and a fifth transistor electrically connected in series,
wherein:
gates of the fourth transistor and the fifth transistor are electrically connected to each other;
drains of the fourth transistor and the fifth transistor are each electrically connected to a gate of the first transistor;
sources of the first transistor and the fifth transistor are each electrically connected to a first power source;
a source of the third transistor is electrically connected to a second power source;
a first signal is inputted to a source of the fourth transistor;
a second signal is inputted to a gate of the second transistor; and
the first signal is different from the second signal.
2. A clocked inverter according to claim 1, wherein:
the first power source is a high potential power source;
the second power source is a low potential power source;
the first transistor and the fifth transistor are each a P-type transistor; and
the second to fourth transistors are each an N-type transistor.
3. A clocked inverter according to claim 1, wherein:
the first power source is a low potential power source;
the second power source is a high potential power source;
the first transistor and the fifth transistor are each an N-type transistor; and
the second to fourth transistors are each a P-type transistor.
4. A clocked inverter according to claim 1, wherein the fourth transistor is replaced with an analog switch.
5. A clocked inverter comprising:
first to third transistors electrically connected in series,
a fourth transistor and a fifth transistor electrically connected in series, and
a sixth transistor and a seventh transistor electrically connected in series, wherein:
gates of the fourth transistor and the fifth transistor are electrically connected to each other;
drains of the fourth transistor and the fifth transistor are each electrically connected to a gate of the first transistor;
gates of the sixth transistor and the seventh transistor are electrically connected to each other;
drains of the sixth transistor and the seventh transistor are each electrically connected to a gate of the third transistor;
sources of the first transistor and the fifth transistor are each electrically connected to a first power source;
sources of the third transistor and the seventh transistor are each electrically connected to a second power source;
a first signal is inputted to a source of the fourth transistor;
a second signal is inputted to a source of the sixth transistor; and
the first signal is different from the second signal.
6. A clocked inverter according to claim 5, wherein:
the first power source is a high potential power source;
the second power source is a low potential power source;
the first transistor, the second transistor, the fifth transistor, and the sixth transistor are each a P-type transistor; and
the third transistor, the fourth transistor, and the seventh transistor are each an N-type transistor.
7. A clocked inverter according to claim 5, wherein:
the first power source is a low potential power source;
the second power source is a high potential power source;
the second transistor, the third transistor, the fourth transistor, and the seventh transistor are each an N-type transistor; and
the first transistor, the fifth transistor, and the sixth transistor are each a P-type transistor.
8. A clocked inverter according to claim 5, wherein the fourth transistor is replaced with an analog switch.
9. A NAND comprising:
a first transistor and a second transistor;
a third transistor; and
a fourth transistor and a fifth transistor electrically connected in series, wherein:
a drain of the first transistor is electrically connected to a drain of the second transistor and a drain of the third transistor;
gates of the fourth transistor and the fifth transistor are electrically connected to each other;
drains of the fourth transistor and the fifth transistor are each electrically connected to a gate of the third transistor;
sources of the first transistor and the second transistor are each electrically connected to a first power source; and
sources of the third transistor and the fifth transistor are each electrically connected to a second power source.
10. A NAND according to claim 9, wherein:
the first power source is a high potential power source;
the second power source is a low potential power source; and
the first transistor, the second transistor, and the fourth transistor are each a P-type transistor, and the third transistor and the fifth transistor are each an N-type transistor.
11. A NAND according to claim 9, wherein the fourth transistor is replaced with an analog switch.
12. A NOR comprising:
a first transistor and a second transistor;
a third transistor; and
a fourth transistor and a fifth transistor electrically connected in series, wherein:
a drain of the first transistor is electrically connected to a drain of the second transistor and a drain of the third transistor;
gates of the fourth transistor and the fifth transistor are electrically connected to each other;
drains of the fourth transistor and the fifth transistor are each electrically connected to a gate of the third transistor;
sources of the first transistor and the second transistor are each electrically connected to a first power source; and
sources of the third transistor and the fifth transistor are each electrically connected to a second power source.
13. A NOR according to claim 12, wherein:
the first power source is a low potential power source;
the second power source is a high potential power source; and
the first transistor, the second transistor, and the fourth transistor are each an N-type transistor, and the third transistor and the fifth transistor are each a P-type transistor.
14. A NOR according to claim 12, wherein the fourth transistor is replaced with an analog switch.
15. A shift register comprising:
a clocked inverter including a first transistor and a second transistor electrically connected in series; and
a third transistor and a fourth transistor electrically connected in series, and
a fifth transistor and a sixth transistor electrically connected in series,
wherein:
gates of the third transistor and the fourth transistor are electrically connected to each other,
drains of the third transistor and the fourth transistor are each electrically connected to a gate of the first transistor,
sources of the first transistor and the fourth transistor are each electrically connected to a first power source,
sources of the second transistor and the sixth transistor are electrically connected to a second power source,
gates of the fifth transistor and the sixth transistor are each electrically connected to each other,
drains of the fifth transistor and the sixth transistor are each electrically connected to a gate of the second transistor,
a pulse generated at an (n\u22121)th stage is inputted to gates of the third, fourth, fifth and sixth transistors arranged at an n-th stage; and
a clock signal or a pulse generated at an (n\u22122)th stage is inputted to a source of the third transistor arranged at the n-th stage.
16. A shift register according to claim 15, wherein:
the first power source is a high potential power source;
the second power source is a low potential power source;
the first transistor, the fourth transistor, and the fifth transistor are each a P-type transistor; and
the second transistor, the third transistor, and the sixth transistor are each an N-type transistor.
17. A shift register according to claim 15, wherein:
the first power source is a low potential power source;
the second power source is a high potential power source;
the first transistor, the fourth transistor, and the fifth transistor are each an N-type transistor; and
the second transistor, the third transistor, and the sixth transistor are each a P-type transistor.
18. A shift register according to claim 15, wherein the third transistor is replaced with an analog switch.
19. A clocked inverter according to claim 1, wherein each of the first to fifth transistors is a thin film transistor.
20. A clocked inverter according to claim 5, wherein each of the first to seventh transistors is a thin film transistor.
21. A NAND according to claim 9, wherein each of the first to fifth transistors is a thin film transistor.
22. A NOR according to claim 12, wherein each of the first to fifth transistors is a thin film transistor.
23. A shift register according to claim 15, wherein each of the first to fifth transistors is a thin film transistor.