1. A photoreceiver arrangement with a photoreceiver, comprising:
a photodiode,
a blocking capacitor for high-frequency and a terminal resistance lying at a signal output line of the photodiode,
wherein the photodiode is connected to a first bias connection for the supply with a blocking voltage, and
wherein a second bias connection is connected to the terminal resistance for controlling the potential at the signal output line, and
a further blocking capacitor for the high-frequency-technological earthing of the terminal resistance is provided.
2. The photoreceiver arrangement according to claim 1, wherein the further blocking capacitor lies between the second bias connection and an earth line, and the terminal resistance is connected between the second bias connection and the signal output line.
3. The photoreceiver arrangement according to claim 2, wherein two earth lines are provided for the high-frequency-technological symmetrisation, and the blocking capacitor, the further blocking capacitor and the terminal resistance are respectively divided into two part elements.
4. The photoreceiver arrangement according to claim 1, wherein the terminal resistance is a linear, ohmic resistance.
5. The photoreceiver arrangement according to claim 1, wherein the first bias connection is divided into two part bias connections.
6. The photoreceiver arrangement according to claim 1, wherein the photodiode is designed as a pin-photodiode, MSM-photodiode, avalanche photodiode or as a photoconductor.
7. The photoreceiver arrangement according to claim 1, wherein the photodiode (PD) is integrated vertically or laterally andor is designed as a pin-Mesa diode in waveguide integration.
8. The photoreceiver arrangement according to claim 1, wherein the photodiode, the blocking capacitors, the terminal resistance and the bias connections are integrated on a chip.
9. The photoreceiver arrangement according to claim 1, wherein the photodiode is connected in a manner such that the anode is directed to the signal output line or that the cathode is directed to the signal output line.
10. The photoreceiver arrangement according to claim 1, wherein the signal output line is connected to a downstream circuit, in particular to a demultiplexer or an amplifier, wherein the photodiode with connections, capacitors and resistances and the downstream electronic circuit, are integrated on a chip andor are tightly packaged in a housing.
11. The photoreceiver arrangement according to claim 1, wherein the signal output line is directly connected to a downstream electronic circuit, in particular to a demultiplexer or an amplifier, wherein the photoreceiver and the downstream electronic circuit are arranged in separate chips andor housings.
12. A method for operating a photoreceiver, which converts an optical data flow into a high-frequency output signal, with which a photodiode via a bias connection is supplied on the rear-side with a blocking voltage, the high frequency at the bias connection is blocked by a blocking capacitor connected to the photodiode, and a terminal resistance is connected to the signal output, wherein a second bias connection is provided, to which a potential for the linear control of the potential at the signal output via the terminal resistance is applied, and that a further blocking capacitor is connected between the cold end of the terminal resistance and earth.
13. The method according to claim 11, wherein the potentials at the bias connections are selected depending on the switch direction of the photodiode, wherein the potential at the second bias connection with regard to magnitude, is smaller than that at the first bias connection.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An apparatus for detecting surge voltage, the apparatus comprising:
a voltage distributor configured to generate a driving voltage when an applied surge voltage exceeds a reference surge voltage;
a signal output unit configured to generate an output signal when driven by the generated driving voltage, the signal output unit comprising a current limiting resistor element and a shunt regulator serially connected between two contacts configured to detect the applied surge voltage; and
a surge voltage detection signal output unit configured to output a surge voltage detection signal indicating that the applied surge voltage exceeds the reference surge voltage in response to the output signal from the signal output unit, the surge voltage detection signal output unit a photo coupler connected directly across and in parallel with the current limiting resistor element,
wherein the shunt regulator is connected in parallel with the voltage distributor.
2. The apparatus of claim 1, wherein the voltage distributor serially connects a voltage distribution resistor element to a resistor element between the two contacts and applies the driving voltage to the signal output unit via a common contact between the distribution resistor element and resistor element when the applied surge voltage exceeds the reference surge voltage.
3. The apparatus of claim 1, further comprising a reference surge voltage limiter configured to limit the reference surge voltage.
4. The apparatus of claim 3, wherein the reference surge voltage limiter includes a Zener diode connected between the two contacts.
5. The apparatus of claim 1, further comprising a computing unit configured to:
store surge voltage generation information in response to the output surge voltage detection signal;
determine whether a count of applied surge voltages that exceed the reference surge voltage is greater than a predetermined number; and
provide a warning to a user that the applied surge voltage exceeds the reference surge voltage if the count is greater than the predetermined number.
6. A method for detecting surge voltage, the method comprising:
determining whether an applied surge voltage exceeds a reference surge voltage;
driving a shunt regulator by generating a driving voltage when the applied surge voltage exceeds the reference surge voltage, a current limiting resistor element serially connected to the shunt regulator between two contacts configured to detect the applied surge voltage; and
outputting a surge voltage detection signal indicating that the applied surge voltage exceeds the reference surge voltage in response to driving the shunt regulator, the surge voltage detection signal output by a photo coupler connected directly across and in parallel with the current limiting resistor element,
wherein the driving voltage is generated by a voltage distributor connected in parallel with the shunt regulator.
7. The method of claim 6, further comprising limiting the reference surge voltage by using a Zener diode.
8. The method of claim 6, further comprising:
storing surge voltage generation information in response to the output-surge voltage detection signal;
determining whether a count of applied surge voltages that exceed the reference surge voltage is greater than a predetermined number; and
providing a warning to a user that the applied surge voltage exceeds the reference surge voltage if the count is greater than the predetermined number.