1. A method for delaying memory accesses directed to cache lines associated with transactional execution, comprising:
commencing transactional execution of a block of instructions within a thread executing on a processor;
receiving a request from a requesting thread to perform a memory access involving a cache line, wherein performing the memory access involves copying the cache line back to the requesting thread;
wherein if performing the memory access on the cache line will interfere with the transactional execution and if it is possible to delay the memory access, the method further comprises,
storing copy-back information for the cache line to enable the cache line to be copied back to the requesting thread, and
performing the memory access and copying the cache line back to the requesting thread at a later time when the memory access will not interfere with the transactional execution.
2. The method of claim 1, wherein it is possible to delay an interfering memory access if a commit operation is in the process of committing updates made during the transactional execution to the architectural state of the processor, and if the memory access is directed to a cache line for which a last update made during the transactional execution has not yet been committed to the architectural state of the processor.
3. The method of claim 2, wherein a cache line associated with a delayed memory access is copied back to the requesting thread after the last update to the cache line during the transactional execution is committed to the architectural state of the processor.
4. The method of claim 2, wherein a cache line associated with a delayed memory access is copied back to the requesting thread after all updates that took place during the transactional execution are committed to the architectural state of the processor.
5. The method of claim 2, wherein it is possible to delay an interfering memory access prior to the commit operation; and
wherein if the transactional execution fails prior to the commit operation, the method further involves copying back cache lines for any interfering memory accesses that have been delayed during the transactional execution, wherein the data that is copied back is original cache line data, which has not been modified during the transactional execution.
6. The method of claim 1, wherein if the memory access will interfere with the transactional execution and if it is not possible to delay the memory access, the method further comprises:
discarding changes made during the transactional execution;
allowing the memory access to complete; and
attempting to re-execute the block of instructions.
7. The method of claim 6, wherein discarding changes made during transactional execution involves:
discarding register file changes made during the transactional execution;
clearing load marks from cache lines;
draining store buffer entries generated during the transactional execution; and
clearing store marks from cache lines.
8. The method of claim 1, wherein an interfering memory access can include:
a store by another thread to a cache line that has been load-marked by the thread; and
a load or a store by another thread to a cache line that has been store-marked by the thread.
9. The method of claim 1, wherein commencing transactional execution involves:
saving processor registers;
configuring the processor to load-mark cache lines during loads that take place during transactional execution;
configuring the processor to store-mark cache lines during stores that take place during transactional execution; and
configuring the processor to continually monitor data references from other threads to detect interfering data references.
10. The method of claim 1, wherein if transactional execution completes without encountering an interfering memory access from another thread, the method further comprises:
committing changes made during the transactional execution to the architectural state of the processor; and
resuming normal non-transactional execution of the program past the block of instructions.
11. The method of claim 10, wherein committing changes made during transactional execution involves:
clearing load marks from cache lines;
committing store buffer entries generated during the transactional execution to memory;
wherein if a store buffer entry contains a last update made to a cache line made during the transactional execution, committing the store buffer entry involves unmarking the corresponding cache line; and
committing register file changes made during transactional execution.
12. The method of claim 1, wherein the request to perform the memory access can include:
a request-to-own (RTO) signal; or
a request-to-share (RTS) signal.
13. An apparatus that facilitates delaying memory accesses directed to cache lines associated with transactional execution, comprising:
a transactional execution mechanism configured to commence transactional execution of a block of instructions within a thread executing on a processor;
a request processing mechanism configured to receive a request from a requesting thread to perform a memory access involving a cache line, wherein performing the memory access involves copying the cache line back to the requesting thread;
wherein if performing the memory access on the cache line will interfere with the transactional execution and if it is possible to delay the memory access, the request processing mechanism is configured to,
store copy-back information for the cache line to enable the cache line to be copied back to the requesting thread, and to
perform the memory access and copy the cache line back to the requesting thread at a later time when the memory access will not interfere with the transactional execution.
14. The apparatus of claim 13, wherein it is possible to delay an interfering memory access if a commit operation is in the process of committing updates made during the transactional execution to the architectural state of the processor, and if the memory access is directed to a cache line for which a last update made during the transactional execution has not yet been committed to the architectural state of the processor.
15. The apparatus of claim 14, wherein the request processing mechanism is configured to copy back a cache line associated with a delayed memory access to the requesting thread after the last update to the cache line during the transactional execution is committed to the architectural state of the processor.
16. The apparatus of claim 14, wherein the request processing mechanism is configured to copy back a cache line associated with a delayed memory access to the requesting thread after all updates that took place during the transactional execution are committed to the architectural state of the processor.
17. The apparatus of claim 14, wherein it is possible to delay an interfering memory access prior to the commit operation; and
wherein if the transactional execution fails prior to the commit operation, the request processing mechanism is configured to copy back cache lines for any interfering memory accesses that have been delayed during the transactional execution, wherein the data that is copied back is original cache line data, which has not been modified during the transactional execution.
18. The apparatus of claim 13, wherein if the memory access will interfere with the transactional execution and if it is not possible to delay the memory access, the transactional execution mechanism is configured to:
discard changes made during the transactional execution;
allow the memory access to complete; and to
attempt to re-execute the block of instructions.
19. The apparatus of claim 18, wherein while discarding changes made during the transactional execution, the transactional execution mechanism is configured to:
discard register file changes made during the transactional execution;
clear load marks from cache lines;
drain store buffer entries generated during the transactional execution; and to
clear store marks from cache lines.
20. The apparatus of claim 13, wherein an interfering memory access can include:
a store by another thread to a cache line that has been load-marked by the thread; and
a load or a store by another thread to a cache line that has been store-marked by the thread.
21. The apparatus of claim 13, wherein while commencing transactional execution, the transactional execution mechanism is configured to:
save processor registers;
configure the processor to load-mark cache lines during loads that take place during transactional execution;
configure the processor to store-mark cache lines during stores that take place during transactional execution; and to
configure the processor to continually monitor data references from other threads to detect interfering data references.
22. The apparatus of claim 13, wherein if transactional execution completes without encountering an interfering memory access from another thread, the transactional processing mechanism is configured to:
commit changes made during the transactional execution to the architectural state of the processor; and to
resume normal non-transactional execution of the program past the block of instructions.
23. The apparatus of claim 22, wherein while committing changes made during transactional execution, the transactional processing mechanism is configured to:
clear load marks from cache lines;
commit store buffer entries generated during the transactional execution to memory, wherein if a store buffer entry contains a last update made to a cache line during the transactional execution, committing the store buffer entry involves unmarking the corresponding cache line; and to
commit register file changes made during transactional execution.
24. The apparatus of claim 13, wherein the request to perform the memory access can include:
a request-to-own (RTO) signal; or
a request-to-share (RTS) signal.
25. An computer system that facilitates delaying memory accesses directed to cache lines associated with transactional execution, comprising:
a processor;
a memory;
a transactional execution mechanism within the processor configured to commence transactional execution of a block of instructions within a thread executing on a processor;
a request processing mechanism within the processor configured to receive a request from a requesting thread to perform a memory access involving a cache line, wherein performing the memory access involves copying the cache line back to the requesting thread;
wherein if performing the memory access on the cache line will interfere with the transactional execution and if it is possible to delay the memory access, the request processing mechanism is configured to,
store copy-back information for the cache line to enable the cache line to be copied back to the requesting thread, and to
perform the memory access and copy the cache line back to the requesting thread at a later time when the memory access will not interfere with the transactional execution.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. Hairstyling device (1) comprising two jaws (2, 3), each supporting at one end a treatment surface (10, 11), at least one of which includes a heating element, said jaws (2, 3) being mounted so as to pivot about a hinge (4) at the other end between an open position that allows the hair to be inserted between the two treatment surfaces (10, 11) and a closed position for placing it in contact with the two treatment surfaces (10, 11), said jaws (2, 3) forming two handle halves (5, 6) between the treatment surfaces (10, 11) and the hinge, characterized in that the device (1) includes return means for the handle halves (5, 6), that cause pressure to be applied to the treatment surfaces (10, 11).
2. Hairstyling device (1) according to claim 1, characterized in that the jaws (2, 3) include an intersecting area (9).
3. Hairstyling device (1) according to claim 2, characterized in that the return means of the handle halves (5, 6) include a device (17) for adjusting the pressure applied to the treatment surfaces.
4. Hairstyling device (1) according to claim 3, characterized in that the return means of the handle halves (5, 6) include a compression spring (12).
5. (canceled)
6. Hairstyling device (1) according to claim 1, characterized in that the two hair treatment surfaces are constituted by two smooth plates (10, 11) for straightening the hair.
7-8. (canceled)
9. Hairstyling device (1) according to claim 1, characterized in that the return means of the handle halves (5, 6) include a device (17) for adjusting the pressure applied to the treatment surfaces.
10. Hairstyling device (1) according to claim 1, characterized in that the return means of the handle halves (5, 6) include a compression spring (12).
11. Hairstyling device (1) according to claim 1, characterized in that the two hair treatment surfaces are constituted by two smooth plates (10, 11) for straightening the hair.