1. A method comprising:
assigning, via a processor, a priority to each voicemail in a plurality of voicemails, wherein the priority is based on a call frequency of a caller associated with each voicemail and a transcription request frequency, to yield prioritized voicemails; and
transcribing a highest priority voicemail in the prioritized voicemails.
2. The method of claim 1, wherein the transcription request frequency is a frequency of transcription requests made by a recipient of the plurality of voicemails.
3. The method of claim 1, further comprising repeatedly transcribing a next highest priority untranscribed voicemail message until no further untranscribed voicemail messages remain.
4. The method of claim 1, further comprising:
establishing a priority ranking threshold; and
repeatedly transcribing a next highest priority voicemail message until no further untranscribed voicemail messages remain above the priority ranking threshold.
5. The method of claim 1, further comprising building a voice model of a respective caller while transcribing voicemail messages.
6. The method of claim 1, wherein assigning the priority to each voicemail message is further based on a user profile.
7. The method of claim 1, further comprising generating speaker-specific syllable libraries while transcribing the prioritized voicemail messages.
8. The method of claim 7, further comprising:
receiving a text-based message from a speaker associated with a generated speaker-specific syllable library; and
generating an audible version of the text-based message based on the generated speaker-specific syllable library.
9. A system comprising:
a processor; and
a computer-readable storage medium having instructions stored which, when executed by the processor, cause the processor to perform operations comprising:
assigning a priority to each voicemail in a plurality of voicemails, wherein the priority is based on a call frequency of a caller associated with each voicemail and a transcription request frequency, to yield prioritized voicemails; and
transcribing a highest priority voicemail in the prioritized voicemails.
10. The system of claim 9, wherein the transcription request frequency is a frequency of transcription requests made by a recipient of the plurality of voicemails.
11. The system of claim 9, the computer-readable storage medium having additional instructions stored which result in operations comprising repeatedly transcribing a next highest priority untranscribed voicemail message until no further untranscribed voicemail messages remain.
12. The system of claim 9, the computer-readable storage medium having additional instructions stored which result in operations comprising:
establishing a priority ranking threshold; and
repeatedly transcribing a next highest priority voicemail message until no further untranscribed voicemail messages remain above the priority ranking threshold.
13. The system of claim 9, the computer-readable storage medium having additional instructions stored which result in operations comprising building a voice model of a respective caller while transcribing voicemail messages.
14. The system of claim 9, wherein assigning the priority to each voicemail message is further based on a user profile.
15. The system of claim 9, the computer-readable storage medium having additional instructions stored which result in operations comprising generating speaker-specific syllable libraries while transcribing the prioritized voicemail messages.
16. The system of claim 15, the computer-readable storage medium having additional instructions stored which result in operations comprising:
receiving a text-based message from a speaker associated with a generated speaker-specific syllable library; and
generating an audible version of the text-based message based on the generated speaker-specific syllable library.
17. A computer-readable storage device having instructions stored which, when executed by a computing device, cause the computing device to perform operations comprising:
assigning a priority to each voicemail in a plurality of voicemails, wherein the priority is based on a call frequency of a caller associated with each voicemail and a transcription request frequency, to yield prioritized voicemails; and
transcribing a highest priority voicemail in the prioritized voicemails.
18. The computer-readable storage device of claim 17, wherein the transcription request frequency is a frequency of transcription requests made by a recipient of the plurality of voicemails.
19. The computer-readable storage device of claim 17, having additional instructions stored which result in operations comprising repeatedly transcribing a next highest priority untranscribed voicemail message until no further untranscribed voicemail messages remain.
20. The computer-readable storage device of claim 17, having additional instructions stored which result in operations comprising:
establishing a priority ranking threshold; and
repeatedly transcribing a next highest priority voicemail message until no further untranscribed voicemail messages remain above the priority ranking threshold.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A logic circuit comprising:
a first logic element (\u201cLE\u201d) including a first lookup table (\u201cLUT\u201d), wherein said first LUT is operable to produce a carry from a first set of bits of three numbers; and
a second LE including:
a second LUT, wherein said second LUT is operable to produce a sum from a second set of bits of said three numbers, and
an adder coupled to receive output of said first LUT directly from said first LE, and coupled to said second LUT, wherein said adder is operable to add said carry and said sum; wherein:
said first LE has a first plurality of inputs for bits of said three numbers;
said second LE has a second plurality of inputs for other bits of said three numbers; and
said logic circuit further comprises a set of connections operable to programmably interconnect selected inputs in said first plurality of inputs to selected inputs in said second plurality of inputs, whereby when said set of connections is programmed to interconnect said selected inputs in said first plurality of inputs to said selected inputs in said second plurality of inputs, said logic circuit is operable to add only two numbers.
2. The logic circuit of claim 1 wherein:
said first LUT comprises a first plurality of smaller LUTs;
said second LUT comprises a second plurality of smaller LUTs;
said first plurality of inputs conduct respective bits of said three numbers to respective ones of said smaller LUTs in said first plurality of smaller LUTs; and
said second plurality of inputs conduct respective other bits of said three numbers to respective ones of said smaller LUTs in said second plurality of smaller LUTs.
3. A programmable integrated circuit device comprising:
at least one logic block comprising:
a first logic element (\u201cLE\u201d) including a first lookup table (\u201cLUT\u201d), wherein said first LUT is operable to produce a carry from a first set of bits of three numbers; and
a second LE including:
a second LUT, wherein said second LUT is operable to produce a sum from a second set of bits of said three numbers, and
an adder coupled to receive output of said first LUT directly from said first LE, and coupled to said second LUT, wherein said adder is operable to add said carry and said sum; wherein:
said first LE has a first plurality of inputs for bits of said three numbers;
said second LE has a second plurality of inputs for other bits of said three numbers; and
said at least one logic block further comprises:
a plurality of local conductors serving at least said first LE and said second LE, and
a set of connections operable to programmably interconnect selected inputs in said first plurality of inputs to selected inputs in said second plurality of inputs via selected conductors in said plurality of local conductors, whereby when said set of connections is programmed to interconnect said selected inputs in said first plurality of inputs to said selected inputs in said second plurality of inputs, said logic circuit is operable to add only two numbers.
4. The programmable integrated circuit device of claim 3 wherein:
said first LUT comprises a first plurality of smaller LUTs;
said second LUT comprises a second plurality of smaller LUTs;
said first plurality of inputs conduct respective bits of said three numbers to respective ones of said smaller LUTs in said first plurality of smaller LUTs; and
said second plurality of inputs conduct respective other bits of said three numbers to respective ones of said smaller LUTs in said second plurality of smaller LUTs.
5. A logic block for a programmable integrated circuit device, said logic block comprising:
a plurality of logic modules, each of said logic modules comprising a plurality of logic elements; and
a plurality of local conductors serving said plurality of logic modules; wherein:
each respective one of said logic modules has a respective plurality of inputs intersecting said plurality of local conductors, including a first plurality of inputs for bits of three numbers and a second plurality of inputs for other bits of said three numbers; said logic block further comprising:
a respective less-than-fully populated matrix of interconnections where each said respective plurality of inputs intersects said plurality of local conductors, at least a subset of each said respective less-than-fully populated matrix of interconnections being identical to at least a subset of each other said respective less-than-fully populated matrix of interconnections for at least a subset of said plurality of logic modules, each of said subsets including connections to more than one of said local conductors; wherein:
corresponding inputs of respective logic elements in each logic module in said subset of said plurality of logic modules are programmably connectable to common ones of said local conductors; and
said logic block further comprises a set of connections operable to programmably interconnect selected inputs in said first plurality of inputs to selected inputs in said second plurality of inputs, whereby when said set of connections is programmed to interconnect said selected inputs in said first plurality of inputs to said selected inputs in said second plurality of inputs, said logic block is operable to operate on only two numbers.
6. The logic block of claim 5 wherein each of said logic elements is an adaptive lookup table comprising a plurality of individual lookup tables and a dedicated binary adder circuit associated with said plurality of individual lookup tables.
7. The logic block of claim 6 wherein:
inputs in a first one of said respective plurality of inputs conduct respective bits of three numbers to respective ones of said individual lookup tables in a first one of said logic elements; and
inputs in a second one of said respective plurality of inputs conduct respective bits of said three numbers to respective ones of said individual lookup tables in a second one of said logic elements.
8. The logic block of claim 6 wherein one input of said dedicated binary adder circuit in one of said logic elements is cascaded from another one of said logic elements.
9. The logic block of claim 8 wherein said another one of said logic elements is another logic element in said logic module.
10. The logic block of claim 8 wherein said another one of said logic elements is another logic element in another one of said logic modules.
11. A programmable integrated circuit device comprising:
at least one logic block comprising:
a plurality of logic modules, each of said logic modules comprising a plurality of logic elements; and
a plurality of local conductors serving said plurality of logic modules; wherein:
each respective one of said logic modules has a respective plurality of inputs intersecting said plurality of local conductors, including a first plurality of inputs for bits of three numbers and a second plurality of inputs for other bits of said three numbers; said logic block further comprising:
a respective less-than-fully populated matrix of interconnections where each said respective plurality of inputs intersects said plurality of local conductors, each said respective less-than-fully populated matrix of interconnections being identical to each other said respective less-than-fully populated matrix of interconnections for at least a subset of said plurality of logic modules; wherein:
corresponding inputs of respective logic elements in each logic module in said subset of said plurality of logic modules are programmably connectable to respective identical subsets of said local conductors; and
said logic block further comprises a set of connections operable to programmably interconnect selected inputs in said first plurality of inputs to selected inputs in said second plurality of inputs, whereby when said set of connections is programmed to interconnect said selected inputs in said first plurality of inputs to said selected inputs in said second plurality of inputs, said logic block is operable to operate on only two numbers.
12. The programmable integrated circuit device of claim 11 wherein each of said logic elements is an adaptive lookup table comprising a plurality of individual lookup tables and a dedicated binary adder circuit associated with said plurality of individual lookup tables.
13. The programmable integrated circuit device of claim 12 wherein each said respective less-than-fully populated matrix of interconnections is identical to each other said respective less-than-fully populated matrix of interconnections for corresponding ones of said plurality of individual lookup tables in subset of said plurality of logic modules.
14. The programmable integrated circuit device of claim 12 wherein one input of each said associated dedicated binary adder circuit is cascaded from another one of said logic elements.
15. The programmable integrated circuit device of claim 14 wherein said another one of said logic elements is another logic element in said logic module.
16. The programmable integrated circuit device of claim 14 wherein said another one of said logic elements is another logic element in another one of said logic modules.