1. A clock and data recovery circuit, receiving input serial data and an input clock signal for recovering a clock signal, said clock and data recovery circuit comprising:
a phase detector, receiving the input serial data and the recovered clock signal as input signals, for comparing phases of the received input signals;
a frequency tracking loop for tracking frequency modulation of the input serial data; said frequency tracking loop including a first integrator for integrating result of comparison from said phase detector and a pattern generator;
a phase tracking loop for tracking phase fluctuation of the input serial data; said phase tracking loop including a second integrator for integrating result of comparison from said phase detector; and
a feedback control circuit for feedback-controlling one or both of said first and second integrators;
a phase interpolator, receiving said input clock signal and a control signal and generating the recovered clock signal for output, said phase interpolator variably adjusting the phase of said recovered clock signal;
said phase detector comparing the phase of the input data signal and the phase of the recovered clock signal output from said phase interpolator;
said pattern generator provided in said frequency tracking loop receiving an integrated value of result of phase comparison from said phase detector, for generating and outputting a signal that is for variably setting the phase of the recovered clock signal from said phase interpolator; and
a mixer for generating a signal that is the result of mixing the integrated value in the phase tracking loop, which controls the phase of the recovered clock signal from said phase interpolator in accordance with the integrated value of the result of phase comparison by said phase detector, and the output of said pattern generator in the frequency tracking loop;
wherein the signal generated by said mixer is supplied to said phase interpolator as the control signal;
wherein said first integrator and second integrator are formed by a common integrator shared by said frequency tracking loop and said phase tracking loop, or said first integrator and second integrator separate integrators are provided in said frequency tracking loop and said phase tracking loop respectively; and
wherein said feedback control circuit, monitoring an output from said integrator and variably controlling a parameter of at least one of said integrators based upon result of monitoring, is connected to said common integrator shared by said frequency tracking loop and said phase tracking loop, or is connected to at least one of said first and second integrators provided separately for respective ones of the phase tracking loop and frequency tracking loop.
2. The clock and data recovery circuit according to claim 1, wherein when one loop out of the phase tracking loop and the frequency tracking loop indicates that said one loop is in a stable state, said mixer outputs the control signal, which is for adjusting the phase of the recovered clock signal in said phase interpolator, based upon result of the phase comparison in the other loop.
3. The clock and data recovery circuit according to claim 1, wherein said mixer outputs a control signal, which advances the phase of the recovered clock signal of said phase interpolator, continuously for a prescribed number of clocks if both the result of phase comparison in the frequency tracking loop and the output of said pattern generator in the frequency tracking loop indicate UP, and outputs a control signal, which retards the phase of the recovered clock signal of said phase interpolator, continuously for a prescribed number of clocks if both the result of phase comparison in the phase tracking loop and the output of said pattern generator in the frequency tracking loop indicate DOWN.
4. The clock and data recovery circuit according to claim 1, wherein said integrator comprises a counter, and a parameter of said integrator is number of counts of said counter.
5. The circuit according to claim 4, wherein in a case where said integrator continuously outputs a control signal that retards or advances the phase of one of said two signals input to said phase detector, said feedback controller reduces the number of counts of said counter.
6. The circuit according to claim 4, wherein in a case where said integrator alternately outputs a control signal that retards or advances the phase of one of said two signals input to said phase detector, said feedback controller enlarges the number of counts of said counter.
7. A clock and data recovery circuit, receiving input serial data and an input clock signal for recovering a clock signal, said clock and data recovery circuit comprising:
a phase detector, receiving the input serial data and the recovered clock signal as input signals, for comparing phases of the received input signals;
a frequency tracking loop for tracking frequency modulation of the input serial data; a phase tracking loop for tracking phase fluctuation of the input serial data, said frequency tracking loop including a pattern generator;
said frequency tracking loop and said phase tracking loop sharing an integrator for integrating result of comparison from said phase detector; and
a feedback control circuit for feedback-controlling said integrator
a phase interpolator, receiving said input clock signal and a control signal and generating the recovered clock signal for output, said phase interpolator variably adjusting the phase of the recovered clock signal;
said phase detector, receiving said input data signal and the recovered clock signal from said phase interpolator as input signals, for comparing phases of the received two input signals, detecting lead or lag and outputting a first control signal in accordance with result of detection;
said integrator, receiving the first control signal output from said phase detector, for integrating the received first control signal and outputting a second control signal;
said pattern generator receiving the second control signal from said integrator, for counting the second control signal, detecting, based upon result of counting, a frequency difference between frequency of the data signal and frequency of the input clock signal to said phase interpolator, and outputting a third control signal; and
a mixer, receiving the second control signal from said integrator and the third control signal from said pattern generator, for generating a fourth control signal based upon the second and third control signals, and supplying the fourth control signal to said phase interpolator as said control signal;
said feedback control circuit monitoring an output of said integrator and variably controlling a parameter of said integrator based upon result of monitoring.
8. The clock and data recovery circuit according to claim 7, wherein said integrator comprises a counter, and a parameter of said integrator is number of counts of said counter.
9. A clock and data recovery circuit, receiving input serial data and an input clock signal for recovering a clock signal, said clock and data recovery circuit comprising:
a phase detector, receiving the input serial data and the recovered clock signal as input signals, for comparing phases of the received input signals;
a frequency tracking loop for tracking frequency modulation of the input serial data; said frequency tracking loop including a first integrator for integrating result of comparison from said phase detector and a pattern generator;
a phase tracking loop for tracking phase fluctuation of the input serial data; said phase tracking loop including a second integrator for integrating result of comparison from said phase detector; and
a feedback control circuit for feedback-controlling one or both of said first and second integrators;
a phase interpolator, receiving the input clock signal and a control signal and generating the recovered clock signal for output, said phase interpolator variably adjusting the phase of the recovered clock signal;
said phase detector, receiving the input data signal and the recovered clock signal from said phase interpolator as input signals, for comparing phases of the received two input signals, detecting lead or lag and outputting a first control signal in accordance with result of detection;
said first integrator, receiving the first control signal output from said phase detector, for integrating the received first control signal and outputting a second control signal;
said second integrator, receiving the first control signal output from said phase detector, for integrating the received first control signal and outputting a third control signal;
said pattern generator, receiving the third control signal from said second integrator, for counting the third control signal, detecting, based upon result of counting, a frequency difference between frequency of the data signal and frequency of the input clock signal to said phase interpolator, and outputting a fourth control signal; and
a mixer, receiving the second control signal from said first integrator and the fourth control signal from said pattern generator, for generating a fifth control signal based upon the second and fourth control signals, and supplying the fifth control signal to said phase interpolator as said control signal;
said feedback control circuit monitoring an output of at least one of said first and second interpolators and variably controlling a parameter of said integrator based upon result of monitoring.
10. The clock and data recovery circuit according to claim 9, wherein said integrator comprises a counter, and a parameter of said integrator is number of counts of said counter.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
We claim:
1. A packet network redistributing excess bandwidth for optimized performance of voice and data sessions conducted on the network, comprising:
plurality of client stations connected to the network for conducting voice and data sessions;
each client station including at least one codec for conducting sessions at a selected minimum bandwidth or a preferred bandwidth; and
a Quality of Service (QoS) application executing in the client stations and controlling the redistribution of bandwidth when a new session is set up or an existing session is removed, so that every new session will have at least minimum bandwidth or, reallocating bandwidth to remaining sessions after a removal of a session to increase bandwidth for some sessions.
2. The network of claim 1 further comprising:
session managing apparatus managing bit rate negotiations between client stations conducting voice andor data sessions after addition or removal of voice or data session.
3. The network of claim 1 further comprises:
an application in the client station executing a protocol for minimum bandwidth allocation.
4. The network of claim 1 further comprises:
an application in the client station executing a protocol for preferred bandwidth allocation.
5. The network of claim 1 further comprises:
an application in the session managing apparatus executing a protocol for bit rate negotiation.
6. The network of claim 1 further comprises:
excess bandwidth detection apparatus and apparatus for allocating bandwidth when a new voice or data session is added based on excess bandwidth(a)(preferred bandwidth)(b) where (a) and (b) are bandwidth margin safeguards.
7. The network of claim 1 further comprises:
timing apparatus which determines whether a session removal has occurred within a time period (T).
8. The network of claim 1 further comprises:
excess bandwidth detection apparatus and apparatus for reallocating bandwidth when an existing voice or data session is removed based on excess bandwidth(a)(preferred bandwidth-minimum bandwidth)(b) where (a) and (b) are bandwidth margin safeguards.
9. The network of claim 5 wherein the protocol for bit rate negotiations is ITU-T H.323.
10. A method of redistributing excess bandwidth in a packet network upon the addition of a session, comprising the steps of:
determining whether a session is being added to the network;
determining if the session is at a preferred bandwidth or a minimum bandwidth;
allocating preferred bandwidth to a new session if excess bandwidth available;
negotiating bit rate for the new session with the allocated bit bandwidth;
Applying a Quality of Service (QoS) algorithm to all established voice sessions including the new session; and
determining if all session bandwidth allocations are equal to or greater than their minimum bandwidth upon addition of a session.
11. The method of claim 10 further comprising the step of:
applying the Quality of Service (QoS) algorithm to all established sessions including data sessions if all session bandwidths are not at their minimum bandwidth.
12. The method of claim 10 further comprising the step of:
negotiating the bit rate for the new session and all established sessions with the bandwidth allocation changed.
13. The method of claim 10 further comprising the step of:
allocating bandwidth when a new voice or data session is added based on excess bandwidth(a)(preferred bandwidth)(b) where (a) and (b) are bandwidth margin safeguards.
14. The method of claim 10 further comprising the step of:
executing an ITU-T protocol for bit rate negotiation.
15. A method for redistributing excess bandwidth in a packet network upon removal of a voice or data session, comprising the steps of:
determining whether a session is being removed from the network bandwidth;
determining if a new session is being added when a time period T has not expired;
determining if any encoded session is allocated with minimum bandwidth upon removal of a session;
if none, applying a Quality of Service (QoS) algorithm to all data sessions with excess bandwidth and negotiate the bit rate for the sessions with bandwidth allocation changed;
finding a voice session with the largest minimum bandwidth subscription; determining whether excess bandwidth is >(a)(preferred bandwidth)(b) where positive constants a and b are bandwidth margin safeguards;
allocating preferred bandwidth to voice sessions with minimum bandwidth; and
determining if any excess bandwidth remains.
16. The method of claim 15 further comprising the step of:
determining for the remaining excess bandwidth if any voice sessions, not including those having been considered, are allocated with minimum bandwidth.
17. The method of claim 15 further comprising the step of:
allocating preferred bandwidth in the remaining bandwidth to the voice session with minimum bandwidth.
18. The method of claim 15 further comprising the step of:
negotiating bit rates for the session with bandwidth allocation changed after applying the QoS algorithm to all sessions.
19. The method of claim 15 further comprising the step of:
allocating bandwidth when a new session is removed based on excess bandwidth(a)(preferred bandwidth-minimum bandwidth)(b) where (a) and (b) are bandwidth margin safeguards.
20. The method of claim 15 further comprising the step of:
determining whether a session changed within a time period T.
21. The method of claim 15 further comprising the step of:
executing a protocol for bit rate negotiation.
22. A program medium, executable in a computer system, for redistributing excess bandwidth in a packet network upon the addition of a session, comprising:
program instruction determining whether a session is being added to the network;
program instruction determining if the session is at a preferred bandwidth or a minimum bandwidth;
program instruction allocating preferred bandwidth to a new session if excess bandwidth available;
program instruction negotiating bit rate for the new session with the allocated bit bandwidth;
program instruction applying a Quality of Service (QoS) algorithm to all established encoded sessions including the new session; and
program instruction determining if all session bandwidth allocations are equal to or greater than their minimum bandwidth upon addition of a session.
23. The medium of claim 22 further comprising:
program instructions applying the Quality of Service (QoS) algorithm to all established sessions including non encoded sessions if all session bandwidths are not at their minimum bandwidth B.
24. The medium of claim 22 further comprising:
program instructions negotiating the bit rate for the new session and all established sessions with the bandwidth allocation changed.
25. The medium of claim 22 further comprising:
program instructions allocating bandwidth when a new session is added based on excess bandwidth(a)(preferred bandwidth)(b) where (a) and (b) are bandwidth margin safeguards.
26. A medium, executable in a computer system, for redistributing excess bandwidth in a packet network upon removal of a session, comprising:
program instructions determining whether a session is being removed from the network bandwidth;
program instructions determining if a new session is being added when a time period T has not expired;
program instructions determining if any encoded session is allocated with minimum bandwidth upon removal of a session;
program instructions applying a Quality of Service (QoS) algorithm to all data sessions with excess bandwidth and negotiate the bit rate for the sessions with bandwidth allocation changed;
program instructions finding an encoded session with the largest minimum bandwidth subscription;
program instructions determining whether excess bandwidth is >(a)(preferred bandwidth)(b) where positive constants a and b are bandwidth margin safeguards;
program instructions allocating preferred bandwidth to encoded sessions with minimum bandwidth; and
program instructions determining if any excess bandwidth remains.
27. The medium of claim 26 further comprising:
program instructions determining for the remaining excess bandwidth if any encoded sessions, not including those having been considered, are allocated with minimum bandwidth.
28. The medium of claim 26 further comprising:
program instructions allocating preferred bandwidth in the remaining bandwidth to the encoded session with minimum bandwidth.
29. The medium of claim 26 further comprising:
program instructions negotiating bit rates for the session with bandwidth allocation changed after applying the QoS algorithm to all sessions.
30. The medium of claim 26 further comprising the step of:
program instructions allocating bandwidth when a new session is removed based on excess bandwidth(a)(preferred bandwidth-minimum bandwidth)(b) where (a) and (b) are bandwidth margin safeguards.
31. The medium of claim 26 further comprising:
program instructions determining whether a session changed within a time period T.