1. 2-1-(2,3-dihydro-2-oxo-1H-benzimidazol-5-yl)aminocarbonyl-2-oxopropylazo-benzoic acid
having a \u0394E* (blackwhite) in masstone below 22.0\xb10.7.
2. The compound according to claim 1, wherein the color strength of the compound is 6 to 55%, higher than the color strength of Hostaperm\xae Yellow H4G (Clariant AG) as standard in white reduction (5:95).
3. The compound according to claim 1, characterized by a cubic, or cuboidal particle form.
4. A process for the manufacture of the compound of the formula
comprising
coupling of diazotized anthranilic acid (1-aminobenzene-2-carboxylic acid) with 5-acetoacetylamino-benzimidazolone in an aqueous medium and a thermal after-treatment, wherein the thermal after-treatment is carried out at a pH above 5.5.
5. The process of claim 4, wherein the thermal after-treatment is carried out at a pH of from 6.0 to 7.3.
6. A compound obtained by the process of claim 4.
7. Macromolecular organic materials of natural or synthetic origin pigmented with a compound of claim 1.
8. A compound obtained by the process of claim 5.
9. Macromolecular organic materials of natural or synthetic origin pigmented with a compound of claim 3.
10. Macromolecular organic materials of natural or synthetic origin pigmented with a compound of claim 6.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
We claim:
1. The method of testing a combinational and sequential logic circuit with shift register latches of individual logic units coupled together to form a shift register scan path for testing logic circuits and uncoupled to disable the scan path while the logic circuit is performing its designed logic function, a method for performing self-testing using a multistage generator means to generate testing sequences for the self-testing and multistage data compression means to compress the responses of the logic circuits, the method comprising:
(a) dividing all the logic paths through a logic gate into two groups based on whether signal transit time of their path from a launch latch to a capture latch is faster or slower than a threshold level;
(b) performing simulation testing by shifting a plurality of pseudo random pulse patterns through said paths to detect faults on fault lists for the paths;
(c) determining if a fault occurred during simulation testing in paths with transit times longer than the threshold level and checking off of the fault from the fault list;
(d) checking for a longer path above the threshold with faults unexercised by the simulation testing; and
e) generating a test for the longer path for forcing an untested fault through the longer path.
2. The method of claim 1 including the step of treating the paths in either group as a single path.
3. The method of claim 1 including the step basing the threshold value on an accepted pulse rest time relative to the longest path.
4. The method of claim 3 including the steps of:
(f) treating all paths in the group containing the shorter transit times as tested when the threshold is exceeded in simulation test of step (b); and
(g) treating all paths in the group containing the longer path as tested when the longest path in that group has been tested using the test generated in step (c).
5. The method of claim 4 including the step of not marking off faults detected in path with a transit time shorter than the threshold.
6. The method of claim 5 including the step of marking of a detected fault in the longest path in which it is detected.
7. A computer program on a computer readable medium for testing combinational and sequential logic circuit with shift register latches of individual logic units coupled together to form a shift register scan path for testing the logic circuit and uncoupled to disable the scan path while the logic circuit is performing its designed logic function, a method for performing self-testing using a multistage generator means to generate testing sequences for the self-testing and multistage data compression means to compress the responses of the logic circuits, the program comprising:
(a) software for dividing all the logic paths through a logic gate into two groups based on whether signal transit time of their path from a launch latch to a capture latch is faster or slower than a threshold level;
(b) software for performing simulation testing by shifting a plurality of pseudo random pulse patterns through said paths to detect faults on fault lists for the paths;
(c) software for determining if a fault occurred during simulation testing in paths with transit times longer than the threshold level and checking off of the fault from the fault list;
(d) software for checking for a longer path above the threshold with faults unexercised by the simulation testing; and
e) software for generating a test for the longer path for forcing an untested fault through the longer path.
8. The computer program of claim 7 including software for treating the paths in either group as a single path.
9. The computer program of claim 7 including software for:
(f) treating all paths in the group containing the shorter transit times as tested when the threshold is exceeded in simulation test of step (b); and
(g) treating all paths in the group containing the longer path as tested when the longest path in that group has been tested using the test generated in step (c).
10. The computer program of claim 9 including the step of not marking off faults detected in path with a transit time shorter than the threshold.
11. The computer program of claim 10 including software for marking off a detected fault in the longest path in which it is detected.