1. An input device comprising:
an insulating thin film substrate on which a fixed electrode that includes a capacitance detection electrode and a connection section is formed, and a movable electrode formed of a conductive material, the movable electrode including a displacement section that is disposed on a surface of the thin film substrate opposite to a surface on which the capacitance detection electrode is formed so as to be opposite to the capacitance detection electrode, and deformed by a pressing force in a direction of the capacitance detection electrode; and
a stationary section that is connected to the connection section of the fixed electrode,
the input device detecting a change in capacitance that occurs when the displacement section has been pressed, and
the thin film substrate functioning as an insulating layer that prevents the displacement section from being electrically connected to the capacitance detection electrode even if the displacement section has been deformed.
2. The input device according to claim 1, the movable electrode including a center stationary section, and the displacement section disposed around the center stationary section, the displacement section including a plurality of protrusion sections that protrude toward the capacitance detection electrode, and a distance between an end of a protrusion section among the plurality of protrusion sections and the capacitance detection electrode sequentially increasing toward a periphery of the input device.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A storage circuit, comprising:
a plurality of storage elements comprising groups of storage cells;
control logic for providing read and write access between the storage cells and a storage interface;
a plurality of voltage selection circuits, each having an output coupled to a power supply input of a corresponding one of the plurality of storage array elements and at least two power supply inputs, each coupled to a plurality of power supply voltage sources having differing non-zero voltages, wherein the voltage selection circuits each provide a selected one of the plurality of differing non-zero voltages in response to a corresponding one of a plurality of digital control values; and
a control value storage coupled to each of the voltage selection circuits for supplying the digital control values to the voltage selection circuits, whereby a minimum performance level of a first set of the plurality of the storage elements having a lower performance is assured by selecting a higher one of the differing non-zero voltages for application to the first set, and whereby lower power consumption is provided by selecting a lower one of the differing non-zero power supply voltages for application to a second set of the plurality of storage elements that have a higher performance.
2. The storage circuit of claim 1, wherein the storage cells are arranged in an array of rows and columns, and wherein the storage elements are columns of the array, whereby the digital values select a particular one of the differing voltages to supply to each column of the array.
3. The storage circuit of claim 1, wherein the storage cells are arranged in an array of rows and columns, and wherein the storage elements are columns of the array, whereby the digital values select a particular one of the differing voltages to supply to each row of the array.
4. The storage circuit of claim 1, wherein the storage cells are arranged in multiple sub-arrays, wherein the storage elements are columns of the array, whereby the digital values select a particular one of the differing voltages to supply to each sub-array.
5. The storage circuit of claim 1, wherein the control value storage comprises a storage cell located in each of the storage elements and is accessed by the control logic.
6. The storage circuit of claim 1, wherein the control value storage comprises a storage separate from the storage elements and wherein the storage circuit further comprises a second control logic for accessing the control value storage.
7. The storage circuit of claim 1, wherein the voltage selection circuit includes an input for disabling selection of power supply voltage at the output of the plurality of voltage selection circuits, whereby the storage elements are placed in a power-down state when a signal provided to the input is in a predetermined logic state.
8. The storage circuit of claim 1, wherein the control logic includes redundancy control logic, wherein the storage circuit further includes storage for redundancy control values that select particular cell groups as replacements for groups of cells within each element or selecting replacement of entire elements.
9. A system, comprising:
a processor for executing program instructions; and
one or more storage devices comprising
a plurality of storage elements comprising groups of storage cells,
control logic for providing read and write access between the storage cells and a storage interface,
a plurality of voltage selection circuits, each having an output coupled to a power supply input of a corresponding one of the plurality of storage array elements and at least two power supply inputs, each coupled to a plurality of power supply voltage sources having differing non-zero voltages, wherein the voltage selection circuits each provide a selected one of the plurality of differing non-zero voltages in response to a corresponding one of a plurality of digital control values, and
a control value storage coupled to each of the voltage selection circuits for supplying the digital control values to the voltage selection circuits, whereby a minimum performance level of a first set of the plurality of the storage elements having a lower performance is assured by selecting a higher one of the differing non-zero voltages for application to the first set, and whereby lower power consumption is provided by selecting a lower one of the differing non-zero power supply voltages for application to a second set of the plurality of storage elements that have a higher performance.
10. The system of claim 9, wherein the control value storage is a non-volatile storage within the one or more storage devices.
11. The system of claim 9, wherein the control value storage is a volatile storage within the one or more storage devices, and wherein the system further comprises a memory coupled to the processor for storing program instructions for execution by the processor, wherein the program instructions comprise program instructions for setting the digital control values in the control value storage of each of the one or more storage devices according to a predetermined set of values for each of the one or more storage devices.
12. The system of claim 11, wherein the program instructions further comprise program instructions for reading the digital control values from a media supplied in association with the one or more storage devices.
13. The system of claim 11, wherein the program instructions further comprise program instructions for:
testing the one or more storage devices with a memory exerciser; and
determining a new set for the digital control values from a result of the testing, and wherein the program instructions for setting are executed to store the new set of digital control values in the control value storage of the one or more storage devices.
14. The system of claim 11, further comprising program instructions for:
sensing changes in an environmental state of the system such that performance characteristics of the one or more storage devices is expected to change;
determining a new set for the digital control values from a result of the sensing, and wherein the program instructions for setting are executed to store the new set of digital control values in the control value storage of the one or more storage devices.