1. A computer-implemented method for identifying odd nets in a hierarchical electronic circuit design, comprising:
receiving a very high-speed integrated circuit hardware description language (VHDL) model of an electronic circuit design;
modifying an architecture section of VHDL code of each endpoint component of the VHDL model to connect each inputoutput (IO) of the endpoint component VHDL code to an instance of a snoop VHDL code;
executing a simulation of the VHDL model through a plurality of clock cycles while driving a logical value by the snoop VHDL code and deriving simulation clashes detected by the snoop VHDL code for each IO of the endpoint components; and
extracting an odd net topology for the VHDL model based on the simulation clashes derived from the simulation.
2. The method of claim 1, further comprising configuring the snoop VHDL code having a first latch and a second latch.
3. The method of claim 2, further comprising driving the logical value by the first latch and detecting simulation clashes by the second latch.
4. The method of claim 3, further comprising configuring the first latch of the snoop VHDL code as a self-resetting latch.
5. The method of claim 1, wherein executing the simulation comprises:
selecting a first IO of a first endpoint component;
driving the logical value by a first latch of the snoop VHDL code connected to the first IO for a clock cycle;
detecting a logical value by a second latch of the snoop VHDL code connected to the first IO for the clock cycle; and
identifying a difference between the driven logical value and the detected logical value as a simulation clash.
6. The method of claim 1, further comprising generating a simulation net list indicating nets for each cycle of the executed simulation.
7. The method of claim 6, further comprising filtering the simulation net list based on logical netnames of the VHDL model.
8. A system for identifying odd nets in a hierarchical electronic circuit design, comprising:
a build module for receiving a very high-speed integrated circuit hardware description language (VHDL) model of an electronic circuit design, the build module operable to modify an architecture section of VHDL code of each endpoint component of the VHDL model to connect each inputoutput (IO) of the endpoint component VHDL code to an instance of a snoop VHDL code; and
a simulation module for executing a simulation of the VHDL model through a plurality of clock cycles while driving a logical value by the snoop VHDL code and deriving simulation clashes detected by the snoop VHDL code for each IO of the endpoint components, the simulation module operable to extract an odd net topology for the VHDL model based on the simulation clashes derived from the simulation.
9. The system of claim 8, wherein the snoop VHDL code comprises a first latch and a second latch.
10. The system of claim 9, wherein the simulation module is operable to drive the logical value by the first latch and detect simulation clashes by the second latch.
11. The system of claim 10, wherein the first latch of the snoop VHDL code comprises a self-resetting latch.
12. The system of claim 8, wherein the simulation module is operable to:
select a first IO of a first endpoint component;
drive the logical value by a first latch of the snoop VHDL code connected to the first IO for a clock cycle;
detect a logical value by a second latch of the snoop VHDL code connected to the first IO for the clock cycle; and
identify a difference between the driven logical value and the detected logical value as a simulation clash.
13. The system of claim 8, wherein the simulation module is operable to generate a simulation net list indicating nets for each cycle of the executed simulation.
14. The system of claim 13, wherein the simulation module is operable to filter the simulation net list based on logical netnames of the VHDL model.
15. A computer program product for identifying odd nets in a hierarchical electronic circuit design, the computer program product comprising:
a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code comprising computer readable program code configured to:
receive a very high-speed integrated circuit hardware description language (VHDL) model of an electronic circuit design;
modify an architecture section of VHDL code of each endpoint component of the VHDL model to connect each inputoutput (IO) of the endpoint component VHDL code to an instance of a snoop VHDL code;
execute a simulation of the VHDL model through a plurality of clock cycles while driving a logical value by the snoop VHDL code and deriving simulation clashes detected by the snoop VHDL code for each IO of the endpoint components; and
extract an odd net topology for the VHDL model based on the simulation clashes derived from the simulation.
16. The computer program product of claim 15, wherein the computer readable program code is configured to drive the logical value by a first latch of the snoop VHDL code and detect simulation clashes by a second latch of the snoop VHDL code.
17. The computer program product of claim 15, wherein the computer readable program code is configured to:
select a first IO of a first endpoint component;
drive the logical value by a first latch of the snoop VHDL code connected to the first IO for a clock cycle;
detect a logical value by a second latch of the snoop VHDL code connected to the first IO for the clock cycle; and
identify a difference between the driven logical value and the detected logical value as a simulation clash.
18. The computer program product of claim 15, wherein the computer readable program code is configured to generate a simulation net list indicating nets for each cycle of the executed simulation.
19. The computer program product of claim 18, wherein the computer readable program code is configured to filter the simulation net list based on logical netnames of the VHDL model.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for fabricating a display that comprises:
fabricating a sealing wall having a first height about a periphery of first display structures that have been fabricated on a first substrate;
fabricating a containment wall having a second height about the periphery and outside the sealing wall, the second height being less than the first height;
dispensing a sealing material between the sealing wall and the containment wall;
contacting a second substrate having second display structures to the first substrate; and
setting the sealing material to bond the first and second substrates.
2. The method of claim 1 wherein the step of fabricating a containment wall comprises:
depositing an imprinting material on a substrate;
moving an imprint template towards the first substrate so that the imprinting material coats predetermined portions of a surface of the imprint template and a surface of the first substrate; and
energizing the imprinting material to cause a solid material in the form of a containment wall to be produced therefrom.
3. The method of claim 2 wherein depositing includes depositing a plurality of droplets upon the first substrate.
4. The method of claim 1 wherein the step of fabricating a sealing wall further includes fabricating separation posts having the first height at predetermined locations on a surface of the first substrate.
5. The method of claim 1 wherein the step of fabricating a sealing wall comprises depositing one or more of SiOx, SiNx, SiOxNy, and combinations thereof.
6. The method of claim 1 wherein the step of fabricating a sealing wall and separation posts comprises depositing one or more of SiOx, SiNx, SiOxNy, and combinations thereof.
7. The method of claim 1 wherein the step of fabricating a sealing wall and a containment wall comprises depositing one or more of SiOx, SiNx, SiOxNy, and combinations thereof.
8. The method of claim 2 wherein the step of fabricating a sealing wall comprises depositing one or more of SiOx, SiNx, SiOxNy, and combinations thereof.
9. A display that comprises:
a first substrate including first display structures;
a second substrate including second display structures; and
the first and second substrates being separated by a distance determined by a separation height of separators disposed at predetermined positions within the display;
wherein the first and second substrates are joined by a sealing material disposed between a sealing wall and a containment wall;
wherein the sealing wall has the separation height and is disposed about a periphery of the first and second display structures; and
wherein the containment wall has a height that is less than the separation height and is disposed the periphery and outside the sealing wall.
10. A method for fabricating a display that comprises:
fabricating a sealing wall having a first height about a periphery of first display structures that have been fabricated on a first substrate, a containment wall having a second height about the periphery and outside the sealing wall, the second height being less than the first height, separation posts having the first height at predetermined locations on a surface of the first substrate, and alignment features on the first substrate;
dispensing a sealing material between the sealing wall and the containment wall;
contacting a second substrate having second display structures to the first substrate; and
setting the sealing material to bond the first and second substrates.
11. The method of claim 10 wherein the step of fabricating the containment wall, the sealing wall, the separation posts, and the alignment features comprises:
depositing an imprinting material on a substrate;
moving an imprint template towards the first substrate so that the imprinting material coats predetermined portions of a surface of the imprint template and a surface of the first substrate; and
energizing the imprinting material to cause a solid material in the form of the containment wall, the sealing wall, the separation posts, and the alignment features to be produced therefrom.
12. The method of claim 11 wherein depositing includes depositing a plurality of droplets upon the first substrate.
13. The method of claim 11 wherein the imprinting material is polyimide.