1. An aluminate-based blue phosphor having the formula (M1\u2212xEux)2\u2212zMgzAlyO2+(32)y, wherein:
M is at least one of a divalent metal selected from the group consisting of Ba and Sr; where
0.05<x<0.5;
3\u2266y<8; and
0.8\u2266z\u22661.2;
wherein the phosphor is configured to absorb radiation in a wavelength ranging from about 280 nm to 420 nm, and to emit visible light having a wavelength ranging from about 420 nm to 560 nm.
2. The blue phosphor of claim 1, wherein the host aluminate crystal structure is substantially a hexagonal crystal structure.
3. An aluminate-based blue phosphor having the formula (M1\u2212xEux)2\u2212zMgzAlyO2+(32)y, wherein:
M is at least one of a divalent metal selected from the group consisting of Ba and Sr; where
0.2<x<0.5;
3\u2266y<8; and
0.8\u2266z\u22661.2;
wherein the phosphor is configured to absorb radiation in a wavelength ranging from about 280 nm to 420 nm, and to emit visible light having a wavelength ranging from about 420 nm to 560 nm.
4. An aluminate-based blue phosphor having the formula (M1\u2212xEux)2\u2212zMgzAlyO2+(32)y:D, wherein:
M is at least one of a divalent metal selected from the group consisting of Ba and Sr; where
0.05<x<0.5;
3\u2266y\u226612; and
0.8\u2266z\u22661.2;
wherein D is a halogen selected from the group consisting of fluorine, chlorine, bromine, and iodine
subject to the proviso that compositions of the formula M1\u2212xEuxMgAl10O17 are specifically excluded.
5. An aluminate-based blue phosphor having the formula (M1\u2212xEux)2\u2212zMgzAlyO2+(32)y:D, wherein:
M is at least one of a divalent metal selected from the group consisting of Ba and Sr; where
0.2<x<0.5;
3\u2266y\u226612; and
0.8\u2266z\u22661.2;
wherein D is a halogen selected from the group consisting of fluorine, chlorine, bromine, and iodine
subject to the proviso that compositions of the formula M1\u2212xEuxMgAl10O17 are specifically excluded.
6. The blue phosphor of claim 5, wherein the phosphor is configured to absorb radiation in a wavelength ranging from about 280 nm to 420 nm, and to emit visible light having a wavelength ranging from about 420 nm to 560 nm.
7. An aluminate-based blue phosphor having the formula (M1\u2212xEux)2\u2212zMgzAlyO2+(32)y, wherein:
M is at least one of a divalent metal selected from the group consisting of Ba and Sr; where
0.05<x<0.5;
3\u2266y\u22666; and
0.8\u2266z\u22661.2;
wherein the phosphor is configured to absorb radiation in a wavelength ranging from about 280 nm to 420 nm, and to emit visible light having a wavelength ranging from about 420 nm to 560 nm.
8. The blue phosphor of claim 7, wherein the host aluminate crystal structure is substantially a hexagonal crystal structure.
9. An aluminate-based blue phosphor having the formula (M1\u2212xEux)2\u2212zMgzAlyO2+(32)y, wherein:
M is at least one of a divalent metal selected from the group consisting of Ba and Sr; where
0.2<x<0.5;
3\u2266y\u22666; and
0.8\u2266z\u22661.2;
wherein the phosphor is configured to absorb radiation in a wavelength ranging from about 280 nm to 420 nm, and to emit visible light having a wavelength ranging from about 420 nm to 560 nm.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method, including:
monitoring a single sticky flag bit in a hardware register embedded in a hot plug controller (HPC) to determine an occurrence of at least one operational excursion associated with a peripheral interface card (PIC) to be coupled to the HPC.
2. The method of claim 1, wherein a state of the single sticky flag bit indicates at least one of a hard error or a soft error.
3. The method of claim 2, further including:
asserting an interrupt upon detecting the state of the single sticky flag bit indicating the at least one of a hard error or a soft error.
4. The method of claim 1, further including:
recording a state of the single sticky flag bit during one of a power-up sequence, a power-down sequence, and a selected operational time period of the PIC.
5. The method of claim 1, further including:
detecting the at least one operational excursion associated with the PIC: and
setting the single sticky flag bit in the hardware register embedded in the HPC wherein the single sticky flag bit in the hardware register embedded in the HPC is selected from a plurality of bits in the hardware register embedded in the HPC, and wherein the hardware register embedded in the HPC is associated with the occurrence of the at least one operational excursion associated with the PIC.
6. The method of claim 1, further comprising:
coupling the PIC to the HPC.
7. The method of claim 5, performed during a power-up sequence associated with the PIC.
8. The method of claim 5, further including:
sensing a state of the single sticky flag bit.
9. The method of claim 5, further including:
masking the plurality of bits to flag the at least one operational excursion associated with the PIC.
10. The method of claim 2 further including:
displaying at least one of a soft error condition or a hard error condition upon detecting the at least one of a hard error or a soft error.
11. An apparatus, including:
a controller including a hardware register, wherein the hardware register comprises a single sticky bit to store an indication of at least one operational excursion associated with a peripheral interface card (PIC) bridge communicatively coupled to controller.
12. The apparatus of claim 11, wherein the controller comprises a standard hot plug controller.
13. The apparatus of claim 11, wherein the PIC bridge comprises a peripheral component interconnect (PCI) bridge.
14. The apparatus of claim 11, wherein the controller is included in the PIC bridge.
15. The apparatus of claim 13, further including:
a PCI card to couple to the PCI bridge to provide the at least one operational excursion.
16. A system, including:
a peripheral component interconnect bridge to provide a bus;
a controller communicatively coupled to the bus:
at least one hardware register coupled to the controller to store a sticky bit, wherein the sticky bit indicates a at least one operational excursion associated with the bus; and
a display to couple to the bus to display a content of the at least one hardware register.
17. The system of claim 16, further including:
a processor to couple to the at least one hardware register via an interrupt request line.
18. The system of claim 16, wherein the at least one hardware register comprises:
a first hardware register to couple to the controller to store soft errors; and
a second hardware register to couple to the controller to store hard errors.
19. The system of claim 16, wherein the at least one hardware register comprises a sticky register.
20. An article including a to machine-accessible storage medium having associated information, wherein the information, when accessed, results in a machine performing:
detecting a plurality of operational excursions associated with a peripheral component interconnect card capable of being coupled to a standard hot plug controller;
setting a plurality of sticky bits in a hardware register, the plurality of sticky bits associated with the plurality of operational excursions;
masking the plurality of sticky bits to flag at least one operational excursion selected from the plurality of operational excursions; and
setting a sticky flag bit of the hardware register to flag the at least one operational excursion selected from the plurality of operational excursions.
21. The article of claim 20, wherein the information, when accessed, results in a machine performing:
selectively masking, clearing, and disabling the plurality of sticky bits.
22. The article of claim 20, wherein a state of the sticky flag bit comprises a result of a logical OR operation performed on the plurality of sticky bits.
23. The method of claim 1, wherein the PIC comprises a peripheral component interconnect (PCI) card.
24. The method of claim 1, wherein the HPC comprises a standard hot plug controller (SHPC).