1. A microelectronic package, comprising:
a microelectronic element having a face and a plurality of element contacts thereon, the microelectronic element embodying a greater number of active devices to provide memory storage array function than any other function, the microelectronic element including a plurality of stacked electrically interconnected semiconductor chips;
a substrate having first and second opposed surfaces, the substrate having a set of substrate contacts on the first surface facing the element contacts of the microelectronic element and joined thereto; and
a plurality of terminals on the second surface configured for connecting the microelectronic package with at least one component external to the package, the terminals electrically connected with the substrate contacts and including first terminals arranged at positions within first and second parallel grids, the first terminals of each of the first and second grids being configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element,
wherein the signal assignments of the first terminals in the first grid are a mirror image of the signal assignments of the first terminals in the second grid.
2. The microelectronic package as claimed in claim 1, wherein the plurality of stacked semiconductor chips includes a first semiconductor chip having contacts thereon joined to the substrate contacts and at least one second semiconductor chip overlying a face of the first semiconductor chip remote from the first surface of the substrate and electrically interconnected with the first semiconductor chip.
3. The microelectronic package as claimed in claim 2, wherein at least one of the at least one second semiconductor chip is configured to at least one of: partially or fully decode information received at a contact thereof, or regenerate information received at the contact thereof for transfer to at least one of the first semiconductor chip or to another of the at least one second semiconductor chip.
4. The microelectronic package as claimed in claim 3, wherein at least some of the first and second chips are electrically connected with one another by a plurality of through-silicon vias.
5. The microelectronic package as claimed in claim 2, wherein at least some of the electrical interconnections between the first and second chips are through electrically conductive traces extending along at least one edge of the microelectronic element.
6. The microelectronic package as claimed in claim 2, wherein the first semiconductor chip is configured to regenerate at least some of the command signals, address signals, and clock signals transferred to the at least one second semiconductor chip, and wherein the at least one second semiconductor chip embodies a greater number of active devices to provide memory storage array function than any other function.
7. The microelectronic package as claimed in claim 6, wherein the first semiconductor chip includes a plurality of through-silicon vias electrically connecting the second semiconductor chip with the first semiconductor chip.
8. The microelectronic package as claimed in claim 7, wherein the at least one second semiconductor chip is a plurality of stacked second semiconductor chips overlying one another, at least some of the second semiconductor chips electrically interconnected with one another by through-silicon vias.
9. The microelectronic package as claimed in claim 2, wherein the first semiconductor chip is configured to at least partially decode at least one of address information or command information received at the first terminals for transfer to the at least one second semiconductor chip.
10. The microelectronic package as claimed in claim 2, wherein the first terminals are configured to carry information that controls an operating mode of the microelectronic element, and the first semiconductor chip is configured to at least one of regenerate or at least partially decode the information that controls the operating mode.
11. The microelectronic package as claimed in claim 2, wherein at least some of the electrical interconnections between the first and second chips are through wire bonds.
12. The microelectronic package as claimed in claim 11, wherein a face of the at least one second chip faces away from the first semiconductor chip, and at least some of the wire bonds connect the first chip with contacts on the face of the at least one second semiconductor chip.
13. The microelectronic package as claimed in claim 11, wherein a face of the at least one second chip faces toward the first semiconductor chip, and at least some of the wire bonds connect the first chip with contacts on the face of the at least one second semiconductor chip.
14. The microelectronic package as claimed in claim 2, wherein the substrate has first and second opposed peripheral edges between the first and second opposed surfaces, the first and second edges extending in the first direction, the second surface having first and second peripheral regions adjacent to the first and second edges, respectively, wherein a central region separates the first and second peripheral regions,
the terminals including a plurality of second terminals exposed at the second surface in at least one of the peripheral regions, at least some of the second terminals configured to carry signals other than the address signals.
15. The microelectronic package as claimed in claim 2, wherein the at least one second chip is electrically interconnected with the first chip through a flip-chip electrical interconnection of second contacts at a surface of the second chip facing and joined with first contacts at a surface of the first chip.
16. The microelectronic package as claimed in claim 2, wherein each of the first and second chips embodies a greater number of active devices to provide memory storage array function than any other function.
17. The microelectronic package as claimed in claim 16, wherein the first chip is configured to regenerate at least some of the address information received at the first terminals for transfer to each second chip, and each second chip is not configured to regenerate the address information for transfer to another chip of the first and second chips.
18. The microelectronic package as claimed in claim 16, wherein the first chip is configured to at least partially decode information that controls an operating mode of the microelectronic element received at the first terminals for transfer to each second chip.
19. The microelectronic package as claimed in claim 17, wherein the second semiconductor chip is a plurality of stacked second semiconductor chips.
20. The microelectronic package as claimed in claim 2, wherein the at least one second semiconductor chip’s memory storage array function is implemented in NAND flash, resistive RAM, phase-change memory, magnetic RAM, static RAM, dynamic RAM, spin-torque RAM, or content-addressable memory technology.
21. A microelectronic package, comprising:
first, second, third, and fourth microelectronic elements, each having a face and a plurality of element contacts thereon, the first, second, third, and fourth microelectronic elements embodying a greater number of active devices to provide memory storage array function than any other function;
a substrate having first and second opposed surfaces, the substrate having first, second, third, and fourth sets of substrate contacts on the first surface facing the element contacts of the respective microelectronic elements and joined thereto, the faces of the first, second, third and fourth microelectronic elements being arranged in a single plane parallel to the first surface of the substrate; and
a plurality of terminals on the second surface configured for connecting the microelectronic package with at least one component external to the package, the terminals electrically connected with the substrate contacts and including first terminals arranged at positions within first and second parallel grids, the first terminals of each of the first and second grids being configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within at least one of the first, second, third, and fourth microelectronic elements,
wherein the signal assignments of the first terminals in the first grid are a mirror image of the signal assignments of the first terminals in the second grid.
22. The microelectronic package as claimed in claim 21, wherein the first and second microelectronic elements are electrically connected with the first grid but are not electrically connected with the second grid and the third and fourth microelectronic elements are electrically connected with the second grid but are not electrically connected with the first grid.
23. The microelectronic package as claimed in claim 21, wherein each of the microelectronic elements has parallel first edges extending in the same respective direction parallel to a column of one or more columns of contacts on the respective microelectronic element, and has second edges extending in a direction transverse to the respective direction, the first and second edges of each microelectronic element bounding the face of such microelectronic element, wherein a plane containing one of the first edges of at least one of the microelectronic elements and normal to the face of such microelectronic element intersects the first edges of another of the microelectronic elements.
24. The microelectronic package as claimed in claim 21, wherein each of the microelectronic elements has two parallel first edges extending in the same direction as the columns of contacts on the respective microelectronic element, and two parallel second edges extending in a direction transverse to the first edge, wherein a plane containing either first edge of any one of the microelectronic elements and normal to the face of such microelectronic element intersects the first edge of another of the microelectronic elements.
25. The microelectronic package as claimed in claim 21, wherein each of the microelectronic elements has parallel first edges extending in the same respective direction parallel to a column of one or more columns of contacts on the respective microelectronic element, the first edges of each of the microelectronic elements extend in a first direction, and the first, second, third and fourth microelectronic elements are arranged in a single row extending in a second direction along the first surface of the substrate, the second direction being orthogonal to the first direction.
26. The microelectronic package as claimed in claim 25, further comprising third and fourth grids of the first terminals, wherein the signal assignments of the first terminals in the third grid are a mirror image of the signal assignments of the first terminals in the fourth grid.
27. The microelectronic package as claimed in claim 26, wherein the terminals include second terminals configured to carry information other than the address information, the second terminals being arranged in fifth and sixth parallel grids on the second surface of the substrate, wherein the signal assignments of the second terminals in the fifth grid are a mirror image of the signal assignments of the second terminals in the sixth grid.
28. The microelectronic package as claimed in claim 27, wherein the first and second grids are separated from one another by at least one of the fifth or sixth grids.
29. A microelectronic package, comprising:
a microelectronic element having a face and a plurality of element contacts thereon, the microelectronic element embodying a greater number of active devices to provide memory storage array function than any other function; and
packaging structure including:
a dielectric layer having a surface overlying the face of the microelectronic element and facing away from the face of the microelectronic element, the surface extending between first and second opposed edges of the dielectric layer, and
a plurality of terminals exposed at the surface of the dielectric layer, at least some of the terminals being electrically connected with the element contacts through traces extending along the dielectric layer and metalized vias extending from the traces and contacting the element contacts, the terminals including first terminals arranged at positions within first and second parallel grids, the first terminals of each of the first and second grids being configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element,
wherein the signal assignments of the first terminals in the first grid are a mirror image of the signal assignments of the first terminals in the second grid.
30. A microelectronic package, comprising:
a microelectronic element having a face and a plurality of element contacts thereon, the microelectronic element embodying a greater number of active devices to provide memory storage array function than any other function;
a substrate having first and second opposed surfaces, the substrate having a set of substrate contacts on the first surface facing the element contacts of the microelectronic element and joined thereto; and
a plurality of terminals on the second surface configured for connecting the microelectronic package with at least one component external to the package, the terminals electrically connected with the substrate contacts and including a first set of first terminals arranged in a first individual column and a second set of the first terminals arranged in a second individual column, the first terminals of each of the first and second grids being configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element,
wherein the signal assignments of the first terminals in the first grid are symmetric about an axis extending between the first and second grids with respect to the signal assignments of the first terminals in the second grid.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What we claim is:
1. A process for preparing shellfish for storage comprising the steps of vacuum packing live shellfish within a suitable container and then heating the shellfish to a temperature of between 80 C. and 110 C. and a pressure of between 0.8-2.0 kgfcm2, said temperature and pressure level being sufficiently high to pasteurize the shellfish while preventing substantial expansion of the container yet sufficiently low so as to minimize vaporization of internal juices and preventing substantially all of the shellfish meat from becoming mushy, thereby maintaining substantially all of the natural juices of the shellfish within the shells and maintaining any inadvertently escaped juices to remain in association with the shellfish from which it originated and within said container, said container being suitable for freezing and transport so that both the shellfish and any inadvertent juices remain together during transport.
2. The process of claim 1 further comprising the step of freezing the shellfish within the container.
3. The process of claim 2 wherein the step of freezing the shellfish involves blast freezing.
4. A process for preparing a shellfish product comprising vacuum packing the shellfish while alive, and cooking the vacuum pack containing the shellfish for sufficiently long to pasteurize the shellfish at a pressure that counteracts the tendency of the pack to expand, so as to capture the natural juices of the shellfish and seawater within the shells within the pack.