1. A non-volatile memory disposed on a substrate, the non-volatile memory comprising:
a plurality of active regions defined by a plurality of isolation structures adapted to be disposed in the substrate, the active regions and the isolation structures being extended in a first direction;
a first memory array disposed on the substrate, the first memory array comprising:
a plurality of memory cell columns, each of the memory cell columns comprising:
a plurality of memory cells connected in series with one another and adapted to be disposed on the substrate at the active regions;
a sourcedrain region, adapted to be disposed in the substrate outside the memory cells;
a plurality of select transistors disposed between the sourcedrain region and the memory cells for connecting the memory cells to the sourcedrain region in series;
a plurality of control gate lines extending across the memory cell columns and extended in a second direction orthogonal to the first direction, the control gate lines respectively connecting the memory cells in the second direction in series;
a plurality of first select gate lines extending across the active regions and respectively connecting the select transistors in the second direction in series; and
a plurality of first contacts arranged along the second direction and disposed on the substrate at a side of the first memory array, each of the first contacts extending across the isolation structure and connecting the sourcedrain regions in every two of the adjacent active regions.
2. The non-volatile memory as claimed in claim 1, wherein the active regions are strip-shaped and arranged in parallel with each other.
3. The non-volatile memory as claimed in claim 1 further comprising a second memory array adapted to be disposed on the substrate and being mirror image to the first memory array with respect to the first contacts.
4. The non-volatile memory as claimed in claim 2 further comprising a second memory array adapted to be disposed on the substrate and being mirror image to the first memory array with respect to the first contacts.
5. The non-volatile memory as claimed in claim 3, wherein the second memory array comprises a plurality of second select gate lines symmetrical to the first select gate lines.
6. The non-volatile memory as claimed in claim 5, wherein the distance between the second select gate line adjacent to the first memory array and the first select gate line adjacent to the second memory array is slightly greater than or equal to a width of each of the first contacts in the first direction.
7. The non-volatile memory as claimed in claim 5, wherein the distance between the second select gate line adjacent to the first memory array and the first select gate line adjacent to the second memory array is slightly less than or equal to a width of each of the first contacts in the first direction.
8. The non-volatile memory as claimed in claim 3, wherein the first memory array and the second memory array share the sourcedrain region.
9. The non-volatile memory as claimed in claim 6, wherein the first memory array and the second memory array share the sourcedrain region.
10. The non-volatile memory as claimed in claim 7, wherein the first memory array and the second memory array share the sourcedrain region.
11. The non-volatile memory as claimed in claim 1 further comprising a plurality of second contacts adapted to be disposed on the substrate to be relative to the first memory array, the second contacts and the first contacts being disposed at respective sides of the first memory array.
12. The non-volatile memory as claimed in claim 3, further comprising a plurality of second contacts adapted to be disposed on the substrate to be relative to the first memory array, the second contacts and the first contacts being disposed at respective sides of the first memory array.
13. The non-volatile memory as claimed in claim 9, further comprising a plurality of second contacts adapted to be disposed on the substrate to be relative to the first memory array, the second contacts and the first contacts being disposed at respective sides of the first memory array.
14. The non-volatile memory as claimed in claim 10, further comprising a plurality of second contacts adapted to be disposed on the substrate to be relative to the first memory array, the second contacts and the first contacts being disposed at respective sides of the first memory array.
15. A manufacturing method of a non-volatile memory comprising the steps of:
providing a substrate;
forming a plurality of strip-shaped isolation structures in the substrate to define a plurality of active regions, the isolation structures and the active regions being arranged in parallel with each other and extended in a first direction;
forming a first memory array on the substrate, the first memory array comprising:
a plurality of memory cell columns, each of the memory cell columns comprising:
a plurality of memory cells connected in series with one another and disposed on the substrate at the active regions;
a sourcedrain region, disposed in the substrate outside the memory cells;
a plurality of select transistors disposed between the sourcedrain region and the memory cells to connect the memory cells to the sourcedrain region in series;
a plurality of control gate lines extending across the memory cell columns and extended in a second direction which is intersecting the first direction, the control gate lines respectively connecting the memory cells in the second direction in series;
a plurality of first select gate lines extending across the active regions and respectively connecting the select transistors in the second direction in series; and
forming a plurality of first contacts on the substrate at a side of the first memory array, the first contacts being arranged along the second direction, each of the first contacts connecting the sourcedrain regions in the substrate at every two of the adjacent active regions.
16. The manufacturing method of the non-volatile memory as claimed in claim 15, wherein the first contacts forming step comprises:
forming an inter-layer dielectric layer on the substrate, the inter-layer dielectric layer covering the first memory array;
forming a plurality of contact holes in the inter-layer dielectric layer, each of the contact holes at least exposing a portion of the two sourceregions in every two of the adjacent active regions and exposing the isolation structure sandwiched between the two active regions; and
filling the contact holes with conductive materials.
17. The manufacturing method of the non-volatile memory as claimed in claim 15, further comprising forming a second memory array connected to the first memory array during the formation of the first memory array, the second memory array being mirror symmetrical to the first memory array with respect to the first contacts.
18. The manufacturing method of the non-volatile memory as claimed in claim 17, wherein the second memory array comprises a plurality of second select gate lines formed on the substrate and is symmetrical to the first select gate lines.
19. The manufacturing method of the non-volatile memory as claimed in claim 17, wherein the first memory array and the second memory array share the sourcedrain region.
20. The manufacturing method of the non-volatile memory as claimed in claim 17, after the formation of the first memory array and the second memory array, wherein the first contacts forming step comprises:
forming a mask layer on the substrate to cover the first memory array and the second memory array;
removing a portion of the mask layer and forming a plurality of contact holes at least exposing the sourcedrain region between the first memory array and the second memory array; and
forming the first contacts through self-alignment,
wherein a spacer is formed on sidewalls of the first select gate lines and the second select gate lines, and a material of the mask layer comprises silicon nitride.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A thermoplastic polymer composition comprising (A) 50 to 95% by mass of an aliphatic polyester-based resin and (B) 5 to 50% by mass of a block copolymer comprising (B1) a hard segment block comprising at least one polymer selected from the group consisting of a polyamide, a polyester, a polyolefin and a polyurethane, and (B2) a soft segment block having an ether bond, with the proviso that a total amount of the components (A) and (B) is 100% by mass.
2. A thermoplastic polymer composition according to claim 1, further comprising at least one polymer selected from the group consisting of (C1) a polyester-based resin (except for the components (A) and (B)), (C2) a polyamide-based resin (except for the component (B)), (C3) an acrylic polymer, (C4) a polycarbonate-based resin, (C5) a polyacetal-based resin, (C6) a polyphenylene ether-based resin, (C7) a polyolefin-based resin (except for the component (B)) and (C8) a styrene-based resin, wherein a content of the at least one polymer in the composition is 5 to 260 parts by mass on the basis of 100 parts by mass of the total amount of the aliphatic polyester-based resin (A) and the block copolymer (B).
3. A thermoplastic polymer composition according to claim 1, wherein the aliphatic polyester-based resin (A) is an aliphatic polyester (A1) mainly obtained from 1,4-butanediol and succinic acid.
4. A thermoplastic polymer composition according to claim 1, wherein the aliphatic polyester-based resin (A) is a polylactic acid-based resin (A2).
5. A thermoplastic polymer composition according to claim 1, wherein the aliphatic polyester-based resin (A) is combination of an aliphatic polyester (A1) mainly obtained from 1,4-butanediol and succinic acid, and a polylactic acid-based resin (A2).
6. A thermoplastic polymer composition according to claim 2, wherein the hard segment of the component (B) is a polyurethane, and the styrene-based resin (C8) as the component (C) is a polymer obtained by polymerizing an aromatic vinyl compound with a vinyl cyanide compound in the presence of a rubber polymer.
7. A thermoplastic polymer composition according to claim 2, wherein the hard segment of the component (B) is a polyolefin, and the component (C) is a polyolefin-based resin.
8. A molded product comprising the thermoplastic polymer composition as defined in claim 1.