1. A reed for weaving, wherein a plurality of reed dents, each including a front edge section and a rear edge section, the reed dents having hollow portions for guiding the weft, are arranged such that said hollow portions are communicated with each other so as to form guide grooves for the weft,
wherein the depths of said hollow portions of the reed dents located at least at one end portion in the weft insert direction are made larger than the depths of the hollow portions of other reed dents and, the nearer the central side in the weft insert direction the reed dents are located, the smaller the depths of the hollow portions are made so as to become approximate to the depths of said hollow portions of said other reed dents, and
wherein, in said reed dents at the one end portion, areas including portions corresponding to said hollow portions in said rear edge sections are projected backward, and wherein said rear edge section of said other reed dents are flat such that the dimension of said other reed dents in the forward and backward direction becomes smaller than that of said reed dents having said portion projected backwards.
2. A reed described in claim 1, wherein the vertical dimension between the upper and lower parts of the hollow portions of said reed dents at the one end portion are made larger than the dimension between the upper and lower parts of said hollow portions of said other reed dents and the nearer the central side in the weft insert direction the reed dents are located, the smaller the hollow portions of the reed dents are made.
3. A reed described in claim 1, wherein said reed is a single reed.
4. A reed described in claim 1, wherein said reed is a divided reed.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A vertical Hall sensor comprising:
a first vertical Hall effect region formed in a semiconductor substrate, with a first plurality of contacts arranged at one side of the first vertical Hall effect region;
a second vertical Hall effect region formed in the semiconductor substrate and of a same doping type as the first vertical Hall effect region, with a second plurality of contacts arranged at one side of the second vertical Hall effect region, wherein the second vertical Hall effect region is connected in series with the first vertical Hall effect region regarding a power supply to the first and second vertical Hall effect regions;
a first layer adjacent to the first vertical Hall effect region at a side other than a side of the first plurality of contacts, having different doping properties than the first vertical Hall effect region, and insulating the first vertical Hall effect region from a bulk of the semiconductor substrate by at least one reverse-biased p-n junction during an operation of the vertical Hall sensor; and
a second layer adjacent to the second vertical Hall effect region at a side other than a side of the second plurality of contacts, having different doping properties than the second vertical Hall effect region, and insulating the second vertical Hall effect region from a bulk of the semiconductor substrate by at least one reverse-biased p-n junction during an operation of the vertical Hall sensor.
2. The vertical Hall sensor according to claim 1, wherein the first layer and the second layer have a higher doping level than the first vertical Hall effect region and the second vertical Hall effect region, respectively.
3. The vertical Hall sensor according to claim 2, wherein the first layer is adjacent to a bulk of the semiconductor substrate at a side opposite to the first vertical Hall effect region and wherein the second layer is adjacent to the bulk of the semiconductor substrate at a side opposite to the second vertical Hall effect region.
4. The vertical Hall sensor according to claim 2, wherein the first layer and the second layer are at least one of: an n-buried layer, two separate portions of an n-buried layer, a p-buried layer, and two separate portions of a p-buried layer.
5. The vertical Hall sensor according to claim 1, further comprising a deep trench isolation that extends to a depth into the semiconductor substrate at which the first and second layers are located, in order to electrically isolate the first vertical Hall effect region and the first layer from the second vertical Hall effect region and the second layer.
6. The vertical Hall sensor according to claim 1, wherein the first layer and the second layer have a different doping type than the first vertical Hall effect region and the second vertical Hall effect region, and wherein the vertical Hall sensor further comprises:
a first additional layer between the first layer and the bulk of the semiconductor substrate for electrically insulating the first layer from the bulk of the semiconductor substrate;
a second additional layer between the second layer and the bulk of the semiconductor substrate for electrically insulating the second layer from the bulk of the semiconductor substrate;
a first electrical connection between the first layer and a first circuit node of a power supply-related series connection of the first and second vertical Hall effect regions, the first circuit node being electrically situated between the first and second vertical Hall effect regions; and
a second electrical connection between the second layer and a second circuit node of the power supply-related series connection, the second circuit node being electrically situated between the second vertical Hall effect region and a low supply potential.
7. The vertical Hall sensor according to claim 6, wherein the first additional layer is electrically connected to the first circuit node and the second additional layer is electrically connected to the second circuit node.
8. The vertical Hall sensor according to claim 6, further comprising:
a first n-throw switch element connected on an n-throw side to at least two contacts the first plurality of contacts and on a common terminal side to the first circuit node; and
a second n-throw switch element connected on a common terminal side to the first circuit node and on an n-throw side to at least two contacts of the second plurality of contacts.
9. The vertical Hall sensor according to claim 1, further comprising a third vertical Hall effect region with a third plurality of contacts and a fourth vertical Hall effect region with a fourth plurality of contacts, the third and fourth vertical Hall effect regions being connected in series with the first and second vertical Hall effect regions regarding the power supply to the first, second, third, and fourth Hall effect regions.
10. The vertical Hall sensor according to claim 9, wherein contacts of the first, second, third, and fourth pluralities of contacts are interconnected with each other so that each of the first, second, third, and fourth Hall effect regions is operated in a different clock phase of a four-phase spinning current scheme.
11. The vertical Hall sensor according to claim 1, wherein the first and second vertical Hall effect regions form a first series connection, and wherein the vertical Hall sensor further comprises a second series connection of at least two vertical Hall effect regions.
12. The vertical Hall sensor according to claim 11, wherein the first and second series connections are connected in parallel to a pair of power supply terminals.
13. The vertical Hall sensor according to claim 11, wherein the vertical Hall effect regions of the first series connection and the second series connection are operated according to a spinning current scheme having at least three clock phases, and wherein a spinning direction for the vertical Hall effect regions of the first series connection is opposite to a spinning direction for the vertical Hall effect regions of the second series connection.
14. The vertical Hall sensor according to claim 13, wherein the spinning direction for the vertical Hall effect regions of the first and second series connections is changed with a spinning direction frequency that is less than or equal to half a spinning scheme frequency of the spinning current scheme.
15. The vertical Hall sensor according to claim 1, wherein the first vertical Hall effect region is operated according to a spinning current scheme with a first spinning direction and the second vertical Hall effect region is operated according to a spinning current scheme with a second spinning direction.
16. The vertical Hall sensor according to claim 1 comprising a buried layer extending at a certain depth within the semiconductor substrate substantially across the entire area of the semiconductor substrate.
17. The vertical Hall sensor according to claim 16, wherein the first layer and the second layer are formed of a continuous portion of the buried layer or wherein the first layer and the second layer are formed of different portions of the buried layer electrically isolated against each other.