1. A processor, comprising:
an instruction issue unit configured to issue vector program instructions for execution, where each vector program instruction operates on one or more vectors, each vector including a plurality of data elements, wherein each vector program instruction operates on one of a plurality of possible element sizes, wherein the plurality of possible element sizes includes a maximum element size; and
a functional unit configured to receive a single instance of a given vector program instruction that operates on the maximum element size, and to concurrently operate on a plurality of data elements of the given vector program instruction having the maximum element size;
wherein the functional unit is further configured to concurrently receive a plurality of vector program instructions that each operate on an element size that is less than the maximum element size, and to concurrently operate on data elements of two or more of the plurality of vector program instructions that operate on less than the maximum element size, such that the plurality of vector program instructions share execution resources of the functional unit that would be underutilized by execution of a single vector program instruction that operates on less than the maximum element size; and
wherein a maximum number of data elements per vector on which the functional unit is configured to concurrently operate is independent of a number of vector program instructions the functional unit is configured to concurrently execute.
2. The processor of claim 1, wherein the vector program instructions are defined according to the Macroscalar instruction set architecture.
3. The processor of claim 1, wherein for at least two of the two or more of the plurality of vector program instructions having less than the maximum element size, the at least two vector program instructions implement different computational operations.
4. The processor of claim 1, wherein for at least two of the two or more of the plurality of vector program instructions having less than the maximum element size, the at least two vector program instructions execute with different latencies.
5. The processor of claim 1, wherein for at least two of the two or more of the plurality of vector program instructions having less than the maximum element size, the at least two vector program instructions operate on data elements of different sizes.
6. The processor of claim 1, wherein the functional unit comprises a plurality of subunits, and wherein at least two of the two or more of the plurality of vector program instructions having less than the maximum element size execute in different subunits.
7. The processor of claim 6, wherein the plurality of subunits includes at least an integer subunit and a floating-point subunit.
8. A method, comprising:
performing, by a processor:
issuing vector program instructions for execution, where each vector program instruction operates on one or more vectors, each vector including a plurality of data elements, wherein each vector program instruction operates on one of a plurality of possible element sizes, wherein the plurality of possible element sizes includes a maximum element size;
for a single instance of a given vector program instruction that operates on the maximum element size, concurrently operating on a plurality of data elements of the given vector program instruction having the maximum element size;
for a plurality of vector program instructions that each operate on an element size that is less than the maximum element size, concurrently operating on data elements of two or more of the plurality of vector program instructions that operate on less than the maximum element size, such that the plurality of vector program instructions share execution resources of the functional unit that would be underutilized by execution of a single vector program instruction that operates on less than the maximum element size;
wherein a maximum number of data elements per vector on which concurrently operation can be performed is independent of a number of vector program instructions that are concurrently executable.
9. The method of claim 8, wherein the vector program instructions are defined according to the Macroscalar instruction set architecture.
10. The method of claim 8, wherein for at least two of the two or more of the plurality of vector program instructions having less than the maximum element size, the at least two vector program instructions implement different computational operations.
11. The method of claim 8, wherein for at least two of the two or more of the plurality of vector program instructions having less than the maximum element size, the at least two vector program instructions execute with different latencies.
12. The method of claim 8, wherein for at least two of the two or more of the plurality of vector program instructions having less than the maximum element size, the at least two vector program instructions operate on data elements of different sizes.
13. The method of claim 8, wherein the vector program instructions are issued to a functional unit comprises a plurality of subunits, and wherein at least two of the two or more of the plurality of vector program instructions having less than the maximum element size execute in different subunits.
14. A system, comprising:
a memory; and
a processor coupled to the memory, wherein the processor comprises:
an instruction issue unit configured to issue vector program instructions for execution, where each vector program instruction operates on one or more vectors, each vector including a plurality of data elements, wherein each vector program instruction operates on one of a plurality of possible element sizes, wherein the plurality of possible element sizes includes a maximum element size; and
a functional unit configured to receive a single instance of a given vector program instruction that operates on the maximum element size, and to concurrently operate on a plurality of data elements of the given vector program instruction having the maximum element size;
wherein the functional unit is further configured to concurrently receive a plurality of vector program instructions that each operate on an element size that is less than the maximum element size, and to concurrently operate on data elements of two or more of the plurality of vector program instructions that operate on less than the maximum element size, such that the plurality of vector program instructions share execution resources of the functional unit that would be underutilized by execution of a single vector program instruction that operates on less than the maximum element size; and
wherein a maximum number of data elements per vector on which the functional unit is configured to concurrently operate is independent of a number of vector program instructions the functional unit is configured to concurrently execute.
15. The system of claim 14, wherein the vector program instructions are defined according to the Macroscalar instruction set architecture.
16. The system of claim 14, wherein for at least two of the two or more of the plurality of vector program instructions having less than the maximum element size, the at least two vector program instructions implement different computational operations.
17. The system of claim 14, wherein for at least two of the two or more of the plurality of vector program instructions having less than the maximum element size, the at least two vector program instructions execute with different latencies.
18. The system of claim 14, wherein for at least two of the two or more of the plurality of vector program instructions having less than the maximum element size, the at least two vector program instructions operate on data elements of different sizes.
19. The system of claim 14, wherein the functional unit comprises a plurality of subunits, and wherein at least two of the two or more of the plurality of vector program instructions having less than the maximum element size execute in different subunits.
20. The system of claim 19, wherein the plurality of subunits includes at least an integer subunit and a floating-point subunit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A toroidal type continuous variable speed transmission, comprising:
an input side disk and an output side disk sharing the same center, each having a circular concave, the inner faces of said disks opposing each other, and each being rotatably supported;
a plurality of trunnions rocking around axes, each axis being skew with respect to the central axis of the input side disk and output side disk;
displacement shafts supported at middle parts of the respective trunnions so as to project from the inner faces of the trunnions;
power rollers each of which has a spherically convex circumferential face and is supported rotatably around the displacement shaft, the power rollers being positioned at the inner face side of the respective trunnions and put between the input side disk and the output side disk;
hydraulic actuators each of which is provided on each trunnion the hydraulic actuator varying the gear ratio between the input side disk and the output side disk by a rocking displacement of the trunnion about the axis caused by an axial displacement of the axis of the trunnion; and
a control valve for switching the feedingdischarging state of pressurized oil to and from each of the hydraulic actuators,
wherein a precess cam is fixed to a member to be displaced together with one of the trunnions;
wherein the motion of the trunnion is transmitted to the control valve by a feedback mechanism for transmitting the displacement of the precess cam to the control valve via a link arm to make possible switching of the feedingdischarging state by this control valve; and
wherein the position of contact between the precess cam and the link arm is closer to the input side disk than the central axis of the trunnion provided with the precess cam is.
2. The toroidal type continuous variable speed transmission according to claim 1, wherein the toroidal type continuous variable speed transmission is incorporated into a continuous variable speed transmission apparatus,
wherein the continuous variable speed transmission apparatus comprises:
an input shaft connected to a driving force source and rotationally driven by the driving force source;
an output shaft for taking out power deriving from the rotation of the input shaft;
a planetary gear mechanism including a sun gear, ring gears arranged around the sun gear, and planetary gears engaged with the sun gear and the ring gears, the planetary gears being arranged between the sun gear and the ring gears and rotatably supported by a carrier rotatably supported concentrically with the sun gear;
a first power transmission path for transmitting power, which is inputted to the toroidal type continuous variable speed transmission, the planetary gear mechanism and said input shaft, via the toroidal type continuous variable speed transmission; and
a second power transmission path for transmitting power inputted to said input shaft without the toroidal type continuous variable speed transmission;
wherein the planetary gear mechanism makes power fed via said first power transmission path and power fed via said second power transmission path transmissible to two items out of said sun gear, said ring gears and said carrier and couples said output shaft with the remaining one item,
wherein mode switching member is provided to switch to and from a state in which power inputted to said input shaft is fed to said planetary gear mechanism via said first power transmission path and said second power transmission path,
and wherein the mode switching member performs switching at least between a first mode in which power is transmitted over said first power transmission path alone and a second mode in which power is transmitted over both the first power transmission path and the second power transmission path.