1. A method for producing an electronic GaAs detector for X-ray detection for imaging, wherein an epitaxial layer is grown on a substrate n+ (or p+) to form a semiconductor material, which includes a predetermined residual doping, wherein a thickness of the substrate is reduced by mechanical-chemical polishing, wherein a p+in+ structure is formed by implanting ions p+ (or n+) on an external face of the semiconductor material, wherein said p+in+ structure is annealed at a temperature 01 for a duration ti, and wherein ohmic contacts are disposed on both faces of the p+in+ structure, wherein individual detectors are produced by masking, passivation and chemical pickling, said method comprises the following steps:
providing parallelism and thermal insulation between the substrate n+ (or p+) and a source material, wherein said source material is a wafer cut into an ingot of semi-insulating GaAs non-intentionally doped, said source material and said semiconductor material being of the same material;
heating said source material to a temperature T1>600\xb0 C.;
heating said substrate n+ (or p+) to a temperature T2<T1;
chemically interacting a reactive gas with the source material of temperature T1 to create volatile products; and
transporting said volatile products to said substrate n+ (or p+) by a pressure gradient between said heated source material and said heated substrate n+ (or p+);
chemically interacting said volatile products at the surface of said substrate n+ (or p+) at temperature T2 to recompose said reactive gas and the semiconductor material,
wherein a resulting thickness of the epitaxial layer is attained that is sufficient to efficiently absorb X photons.
2. The method according to claim 1, wherein the ohmic contacts are produced by first evaporating a gold-based alloy.
3. The method according to claim 1 or 2, wherein said the residual doping is reduced by uniform irradiation with 1 MeV electrons and at an adjusted dose, and wherein the adjustment of said dose is performed by measuring a capacity of an individual detector according to the dose and stopping the irradiation when the capacity is equal to that of the thickness of the epitaxial layer.
4. The method according to claim 1 or 2, wherein the thickness of the epitaxial layer depends on an energy of the X photons to be absorbed, but ranges between 100 \u03bcm and 1 mm.
5. The method according to claim 1 or 2, wherein the reactive gas is H2O under a partial pressure of several hundred ppm.
6. The method according to claim 1 or 2, wherein growth of the epitaxial layer is performed under purified hydrogen atmosphere at atmospheric pressure.
7. A device for producing an electronic GaAS detector for X-ray detection for imaging comprising:
a chamber;
k feet (with k\u22673) forming a tripod and thermally insulating the chamber from a remainder of the device;
a first plate mounted on the tripod and serving as a base for the remainder of the device;
a first inert plate;
a first wafer comprising a first duct which accommodates a first temperature measuring means therein;
heating means which includes a first power supplied heater and heats a substrate n+ (or p+) to a temperature T2>600\xb0 C., said heating means being thermally insulated from said first plate by said first inert plate;
an inert ring which separates and thermally insulates the substrate n+ (or p+) and a source material;
a second power supplied heater which heats the source material to a temperature T1>T2;
a second wafer comprising a second duct which accommodates a second temperature measuring means therein; and
a second inert plate which thermally insulates a second plate from the remainder of the device.
8. The device according to claim 7, wherein parallelism between the source material and the substrate n+ (or p+) is maintained to be in excess of within 0.1 mm by the inert ring.
9. The device according to claim 7 or 8, wherein the inert ring enables gaseous permeability between a space where reactions take place and an internal atmosphere of the device, said atmosphere being composed of purified H2 containing H2O at a controlled pressure.
10. The device according to claim 7 or 8, wherein the chamber is evacuated by a pump before the purified H2 is introduced and after deposition of the epitaxial layer in order to filter products derived from such a reaction.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of writing NAND flash memory, comprising:
sequentially providing write data to a first secondary data cache and a second secondary data cache;
storing data from the first secondary data cache in a first primary data cache;
storing the data from the second secondary data cache in a second primary data cache; and
writing data from a first primary data cache into a first block of flash memory and from a second primary data cache into a second block of flash memory simultaneously;
wherein storing data from the first and second primary data caches into the first and second blocks of flash memory occurs while new write data is sequentially provided to the first and second secondary data caches.
2. The method of writing NAND flash memory of claim 1, the first and second and blocks of flash memory comprising different pages.
3. The method of writing NAND flash memory of claim 2, wherein the first and second pages are sequential pages in memory.
4. The method of writing NAND flash memory of claim 1, wherein the sequentially provided write data is provided sequentially via a multiplexer.
5. The method of writing NAND flash memory of claim 1, wherein storing data from the first secondary data cache in the first primary data cache and storing data from the second secondary data cache in the second primary data cache occurs only after data previously stored in the first and second primary data caches has been written to memory.
6. The method of writing NAND flash memory of claim 4, wherein sequentially providing write data via the multiplexer comprises receiving the write data in the multiplexer via an input of the flash memory.
7. A NAND flash memory controller, comprising:
a first secondary data cache operable to store data;
a second secondary data cache operable to store data;
a first primary data cache operable to store data received from the first secondary data cache, and coupled to a first block of flash memory and operable to store data to the first block of flash memory;
a second primary data cache operable to store data received from the second secondary data cache, and coupled to a second block of flash memory and operable to store data to the second block of flash memory;
an input coupled to the first secondary data cache and second secondary data cache, the input operable to receive write data and sequentially output write data to the first secondary data cache and the second secondary data cache;
wherein writing data from the first and second primary write caches into the first and second blocks of memory occurs while new write data is sequentially provided to the first and second secondary data caches via the input.
8. The NAND flash memory controller of claim 7, wherein the first and second and blocks of flash memory comprise different pages.
9. The NAND flash memory controller of claim 8, wherein the first and second pages are sequential pages in memory.
10. The NAND flash memory controller of claim 7, wherein the input comprises a multiplexer, and wherein the sequentially provided write data is provided via the multiplexer.
11. The NAND flash memory controller of claim 10, further comprising control logic operable to store data from the first secondary data cache in the first primary data cache and store data from the second secondary data cache in the second primary data cache only after data previously stored in the first and second primary data caches has been written to memory.
12. The NAND flash memory controller of claim 7, further operable to output data from the multiplexer at a rate at least twice the approximate write latency rate of a flash memory block.
13. A NAND flash memory device, comprising:
first and second blocks of flash memory;
a first primary data cache coupled to the first block of flash memory and a second primary data cache coupled to the second block of flash memory;
a first secondary data cache coupled to the first primary data cache, and a second secondary data cache coupled to the second primary data cache;
an input operable to selectively write data to the first and second secondary data caches; and
control logic operable to control writing data from the first and second primary data caches to the first and second blocks of flash memory, to control transfer of data from the first and second secondary caches to the first and second primary data caches, and to control selective transfer of data from the input to the first and second secondary data caches, such that writing data from the first and second primary data caches to the first and second blocks of flash memory occurs while new write data is sequentially provided to the first and second secondary data caches via the input.
14. The NAND flash memory device of claim 13, wherein the device comprises at least one of a flash memory card, a computer flash drive, a cellular telephone, a personal digital assistant, or a digital camera.
15. The NAND flash memory device of claim 13, wherein the input comprises a multiplexer and the control logic is further operable to control the multiplexer to alternately transfer write data to the first secondary data cache and second secondary data cache.
16. The NAND flash memory device of claim 15, the control logic further operable to write data from the first primary data cache to the first block of flash memory and to write data from the second primary data cache to the second block of flash memory while the multiplexer alternately outputs data to the first secondary data cache and second secondary data cache.
17. The NAND flash memory device of claim 16, wherein the flash memory controller is further operable to load data from the first secondary data cache into the first primary data cache and to load data from the second secondary data cache into the second primary data cache after data is loaded into the first and second secondary data caches.
18. The NAND flash memory device of claim 13, the multiplexer further operable to output data at a rate at least twice the approximate write latency rate of a flash memory block.
19. The NAND flash memory controller of claim 13, wherein the first block of flash memory and the second block of flash memory comprise sequential flash memory pages.