1. An ottoman device comprising:
a fixing frame positioned beneath a seat;
a leg support folded to and unfolded from a bottom of the seat with respect to the fixing frame with an adjustable angle;
an electric driving device mounted on the fixing frame and providing a rotational force; and
a link device including a link frame, to which the leg support is integrally attached onto, and a plurality of links pivotally coupling the line frame and the fixing frame,
wherein at least one of the plurality of links is coupled to the electric driving device and rotated by the rotational force of the electric driving device to operate the link frame and the leg support.
2. The ottoman device of claim 1, wherein the electric driving device comprises:
a drive motor fixedly mounted on the fixing frame;
a gear box assembled to the drive motor and transmitting a rotational force of the drive motor;
a drive shaft provided co-axially on both lateral sides of an output portion of the gear box and rotated by receiving the rotational force of the drive motor through the gear box; and
a gear device provided at both ends of the drive shaft and operating the link frame and the at least one of the plurality of links as the drive shaft rotates.
3. The ottoman device of claim 2, wherein the gear device comprises:
a drive gear integrally assembled to both ends of the drive shaft; and
a driven gear engaged with the drive gear and connected the at least one of the plurality of links to operate the link device by the rotation of the drive gear.
4. The ottoman device of claim 3, wherein the drive gear and the driven gear are rotatably supported by a gear bracket mounted on a front surface of the fixing frame.
5. The ottoman device of claim 3, wherein one end of the at least one of the plurality of links is coupled to the gear device and the other end thereof is coupled to a lower side of the link frame, and
wherein the other ones of the plurality of links couple the fixing frame and upper side of the link frame.
6. The ottoman device of claim 2, wherein the link device further comprises:
a first link coupling the gear devices formed at both ends of the drive shaft and the link frame; and
a second link coupling the link frame and the fixing frame,
wherein the first link is rotated by the gear device to operate the link frame and, at the same time, the second link on the fixing frame holds both sides of the link frame and rotates.
7. The ottoman device of claim 6, wherein the gear device comprises:
a drive gear integrally assembled to both ends of the drive shaft; and
a driven gear engaged with the drive gear and connected to the first link to operate the link device by the rotation of the drive gear.
8. The ottoman device of claim 7, wherein the drive gear and the driven gear are rotatably supported by a gear bracket mounted on a front surface of the fixing frame.
9. The ottoman device of claim 6, wherein one end of the first link is coupled to the gear device and the other end thereof is coupled to a lower side of the link frame, and
wherein one end of the second link is coupled to the fixing frame and the other end thereof is coupled to an upper side of the link frame.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A method for manufacturing a semiconductor device, comprising the steps of:
a) preparing a semiconductor substrate comprising cell and peripheral areas;
b) forming a gate structure in each of the cell and peripheral areas, the gate structure comprising a gate dielectric, gate electrode and mask pattern;
c) forming a first side wall spacer on each side of each gate structure in the cell and peripheral areas;
d) growing a single crystal silicon layer on exposed portions of the semiconductor substrate by selective epitaxial growth;
e) sequentially forming a first insulating layer and a second insulating layers over the first insulating layer at least covering partially the substrate and the gate structure to form;
Sequentially forming a second side wall spacer covering exposed portions of each first side wall spacer in the peripheral area and a third side wall spacer covering each second side wall spacer;
d) conducting ion implantation on the semiconductor substrate in the peripheral area;
e) removing the second insulating layer in the cell area and the third side wall spacer in the peripheral area;
f) forming an interlayer insulating layer over the cell and peripheral areas;
g) removing the interlayer insulating layer from the cell area, and the second insulating layer from the cell area except the top portion and first side walls of the gate structure in the cell area;
h) forming a conductive layer over the cell area; and
i) planarizing the conductive layer to expose the gate structure in the cell area to form a contact plug in the cell area.
2. The method as recited in claim 1, wherein the first side wall spacer is formed to a thickness in the range of approximately 200 to approximately 500 .
3. The method as recited in claim 1, wherein the single crystal silicon layer is formed to a thickness ranging from 1,000 to 3,000 by doping phosphorous (P) with a dose amount of 5E18 ioncm2 to 5E19 ioncm2.
4. The method as recited in claim 1, wherein the single crystal silicon layer is formed by using a low pressure chemical vapor deposition (LPCVD) or an ultra high vacuum chemical vapor deposition (UHVCVD).
5. The method as recited in claim 4, wherein the low pressure chemical vapor deposition (LPCVD) is carried out for 3 minutes to 10 minutes using a mixed gas of dichlorosilane and HCl on condition at a pressure ranging from 10 Torr to 100 Torr and a temperature ranging from 750 C. to 950 C.
6. The method as recited in claim 5, wherein the low pressure chemical vapor deposition (LPCVD) is carried out using a flux of dichlorosilane and a flux of HCl ranging from approximately 30 sccm to approximately 300 sccm and approximately 30 sccm to approximately 200 sccm, respectively.
7. The method as recited in claim 4, wherein the ultra high vacuum chemical vapor deposition (UHVCVD) is carried out using a silane gas at a temperature ranging from 600 C. to 700 C. and at a pressure in the range of 0 to 1 Torr.
8. The method as recited in claim 1, wherein the first insulating layer has a thickness in the range of 100 to 200 using a nitride layer.
9. The method as recited in claim 1, wherein the second insulating layer has a thickness in the range of 300 to 500 .
10. The method as recited in claim 1, wherein the step of conducting ion implantation includes using boron (B) as a dopant with a dose amount of 1E15 ioncm2 to 1E17 ioncm2 and an implantation energy ranging from 5 KeV to 50 KeV providing that the contact region is a p-type.
11. The method as recited in claim 1, wherein the step of conducting ion implantation includes using BF2 as the dopant with a dose amount of 1E15 ioncm2 to 1E17 ioncm2 and the implantation energy ranging from 10 KeV to 100 KeV providing that the contact region is a p-type.
12. The method as recited in claim 1, wherein the step of conducting ion implantation includes using arsenic (As) as the dopant with a dose amount of 1E15 ioncm2 to 1E17 ioncm2 and the implantation energy ranging from 10 KeV to 100 KeV providing that the contact region is an n-type.
13. The method as recited in claim 1, wherein the step of conducting ion implantation includes using phosphorus (P) as the dopant with a dose amount of 1E15 ioncm2 to 1E17 ioncm2 and the implantation energy ranging from 10 KeV to 70 KeV providing that the contact region is an n-type.
14. The method as recited in claim 1, wherein a contact region in the cell area is formed to a depth in the range of 300 to 800 by diffusion of impurity ions while growing the single crystal silicon layer.
15. The method as recited in claim 1, wherein the step of forming an interlayer insulating layer includes forming it to a thickness in the range of 4,000 to 8,000 using a boron-phophor-silicate-glass (BPSG).
16. The method as recited on claim 1, wherein the step of forming a conductive layer includes forming it to a thickness in the range of 3,000 to 7,000 C. using a P-doped single crystal silicon to a dose amount of 1E19 ioncm2 to 1E21 ioncm2.
17. The method as recited in claim 1, further comprising cleaning the semiconductor substrate using a RCA, UVO3, dipping in fluoric acid (HF) or the combination thereof after forming the first side wall spacer.
18. The method as recited in claim 1, wherein the step of planarizing includes using chemical mechanical polishing (CMP).
19. The method as recited in claim 1, wherein the step of removing the third insulation layer includes using fluoric acid (HF).